Dedizierte massiv parallele Systeme (PARO)

A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors (2009) Dutta H, Kissler D, Hannig F, Kupriyanov O, Teich J, Pottier B Journal article Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis (2009) Dutta H, Hannig F, Teich J Conference contribution Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines (2009) Dutta H, Zhai J, Hannig F, Teich J Conference contribution Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning (2009) Hannig F, Dutta H, Teich J Conference contribution Model-based synthesis and optimization of static multi-rate image processing algorithms (2009) Keinert J, Dutta H, Hannig F, Haubelt C, Teich J Conference contribution, Conference Contribution Scheduling Techniques for High-Throughput Loop Accelerators (2009) Hannig F Thesis Invasive Algorithms and Architectures (2008) Teich J Journal article Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism (2008) Schaffer R, Merker R, Hannig F, Teich J Conference contribution The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications (2008) Hannig F, Ruckdeschel H, Teich J Conference contribution Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices (2008) Dutta H, Hannig F, Ruckdeschel H, Teich J Conference contribution