Dedizierte massiv parallele Systeme (PARO)

Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays (2017) Tanase AP, Witterauf M, Teich J, Hannig F Journal article, Original article A Quick Tour of High-Level Synthesis Solutions for FPGAs (2016) Hannig F Book chapter / Article in edited volumes LoopInvader: A Compiler for Tightly Coupled Processor Arrays (2016) Tanase AP, Witterauf M, Sousa É, Lari V, Hannig F, Teich J Conference contribution Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays (2016) Witterauf M, Tanase AP, Hannig F, Teich J Conference contribution A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators (2016) Bhadouria VS, Tanase AP, Schmid M, Hannig F, Teich J, Ghoshal D Journal article FPGAs for Software Programmers (2016) Koch D, Hannig F, Ziener D Edited Volume Adaptive fault tolerance through invasive computing (2015) Witterauf M, Tanase AP, Teich J, Lari V, Zwinkau A, Snelting G Conference contribution, Conference Contribution A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays (2015) Lari V, Tanase AP, Teich J, Witterauf M, Khosravi F, Hannig F, Meyer B Conference contribution, Conference Contribution Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015) (2015) Hannig F, Koch D, Ziener D Edited Volume Techniques for on-demand structural redundancy for massively parallel processor arrays (2015) Teich J, Lari V, Tanase AP, Witterauf M, Khosravi F, Meyer B Journal article, Original article