Dedizierte massiv parallele Systeme (PARO)

On-demand fault-tolerant loop processing on massively parallel processor arrays (2015) Tanase AP, Witterauf M, Teich J, Hannig F, Lari V Conference contribution, Conference Contribution Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays (2015) Tanase AP, Witterauf M, Hannig F, Teich J Conference contribution, Conference Contribution Symbolic inner loop parallelisation for massively parallel processor arrays (2014) Tanase AP, Witterauf M, Teich J, Hannig F Conference contribution, Conference Contribution Symbolic Mapping of Loop Programs onto Processor Arrays (2014) Teich J, Tanase AP, Hannig F Book chapter / Article in edited volumes Domain-Specific Augmentations for High-Level Synthesis (2014) Schmid M, Tanase AP, Hannig F, Teich J, Bhadouria VS, Ghoshal D Conference contribution Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach (2014) Hannig F, Lari V, Boppu S, Tanase AP, Reiche O Journal article High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model (2014) Schmid M, Hannig F, Tanase AP, Teich J Book chapter / Article in edited volumes Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays (2013) Teich J, Tanase AP, Hannig F Conference contribution Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays (2013) Sousa É, Tanase AP, Hannig F, Teich J Conference contribution Real-Time Range Image Preprocessing on FPGAs (2013) Schmid M, Blocherer M, Hannig F, Teich J Conference contribution