Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Optimal free-space management and routing-conscious dynamic placement for reconfigurable devices (2007) Ahmadinia A, Bobda C, Fekete SP, Teich J, Van Der Veen JC Journal article, Original article Massively Parallel Processor Architectures: A Co-design Approach (2007) Dutta H, Hannig F, Kupriyanov O, Kissler D, Teich J, Schaffer R, Siegel S, et al. Conference contribution An operating system infrastructure for fault-tolerant reconfigurable networks (2006) Koch D, Streichert T, Dittrich S, Strengert C, Haubelt C, Teich J Conference contribution Dynamically Reconfigurable Architectures (2006) Becker J, Teich J, Athanas P, Brebner G Edited Volume A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms (2006) Dutta H, Hannig F, Teich J Other publication type Multi-objective topology optimization for networked embedded systems (2006) Streichert T, Haubelt C, Teich J Conference contribution, Conference Contribution Hardware cost analysis for weakly programmable processor arrays (2006) Kissler D, Hannig F, Kupriyanov O, Teich J Conference contribution, Conference Contribution Stochastic Timing Analysis of Communicating Tasks with Internal State (2006) Teich J Other publication type A Flexible Reconfiguration Manager for the Erlangen Slot Machine (2006) Majer M, Ahmadinia A, Bobda C, Teich J Conference contribution MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I (2006) Kupriyanov O, Hannig F, Kissler D, Schaffer R, Teich J Other publication type