Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

ALPACA: An Accelerator Chip for Nested Loop Programs (2024) Walter D, Brand M, Heidorn C, Witterauf M, Hannig F, Teich J Conference contribution, Conference Contribution ABACUS: ASIP-based Avro Schema-customizable Parser Acceleration on FPGAs (2024) Hahn T, Schüll D, Wildermann S, Teich J Conference contribution, Conference Contribution CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets (2024) Krüger P, Wildermann S, Teich J Conference contribution, Conference Contribution Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems (2024) Letras M, Falk J, Teich J Journal article, Online publication Accelerating DNNs using Weight Clustering on RISC-V Custom Functional Units (2024) Sabih M, Sesli B, Hannig F, Teich J Conference contribution, Conference Contribution SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation (2024) Plagwitz P, Hannig F, Teich J, Keszöcze O Conference contribution, Original article Compiler-based Processor Network Generation for Neural Networks on FPGAs (2024) Plagwitz P, Hannig F, Teich J, Keszöcze O Conference contribution, Original article Estimating the Execution Time of CNN Inference on GPUs (2024) Groth S, Schmid M, Teich J, Hannig F Conference contribution, Original article Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks (2024) Heidorn C, Sabih M, Meyerhöfer N, Schinabeck C, Teich J, Hannig F Journal article Methods for Generating Response Ranges for Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs (2024) Esper K, Wildermann S, Teich J Conference contribution, Original article