Prof. Dr.-Ing. Jürgen Teich

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

2020: HiPEAC 2020 Paper Award HiPEAC Network Jorge Alfonso Echavarria Gutiérrez, Stefan Wilder… 2018: Mitgliedschaft acatech - Deutsche Akademie der Technikwissenschaften acatech - Deutsche Akademie der Technikwissenschaften Jürgen Teich 2016: HiPEAC Paper Award: Formal Reliability Analysis of Switched Ethernet Automotive Networks under Transient Transmission Errors The Steering Committee of the HiPEAC Network of Excellence Jürgen Teich, Fedor Smirnov, Michael Glaß, Felix … 2015: Best Paper Award: Reliability of Space-Grade vs. COTS SRAM-based FPGA in N-Modular Redundancy NASA/ESA Adaptive Hardware and Systems Robert Glein, Florian Rittner, Andreas Becher, Da… 2015: HiPEAC Paper Award: Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures The Steering Committee of the HiPEAC Network of Excellence Sascha Roloff, David Schafhauser, Frank Hannig, J… 2014: HiPEAC Paper Award: A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor The Steering Committee of the HiPEAC Network of Excellence Robert Glein, Bernhard Schmidt, Florian Rittner, … 2014: Best Paper Award: Automatic Graph-based Success Tree Construction and Analysis 60th Annual Reliability and Maintainability Symposium (RAMS 2014) Hananeh Aliee, Michael Glaß, Rolf Wanka, Jürgen T… 2013: Best Paper Award: Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) Jürgen Teich, Alexandru-Petru Tanase, Frank Hannig 2012: HiPEAC Paper Award: Power Management Strategies for Serial RapidIO Endpoints in FPGAs The Steering Committee of the HiPEAC Network of Excellence Moritz Schmid, Frank Hannig, Jürgen Teich 2011: Mitgliedschaft Academia Europaea Academia Europaea Jürgen Teich