Prof. Dr.-Ing. Jürgen Teich



Organisation


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lehrstuhl für Informatik 1 (IT-Sicherheitsinfrastrukturen)


Awards / Honours

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2018 : Mitgliedschaft acatech - Deutsche Akademie der Technikwissenschaften
2016 : HiPEAC Paper Award: Formal Reliability Analysis of Switched Ethernet Automotive Networks under Transient Transmission Errors
2015 : Best Paper Award: Reliability of Space-Grade vs. COTS SRAM-based FPGA in N-Modular Redundancy
2015 : HiPEAC Paper Award: Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures
2014 : Best Paper Award: Automatic Graph-based Success Tree Construction and Analysis



Project lead

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SHARE: SHARE at FAU
Prof. Dr.-Ing. Jürgen Teich
(01/08/2018 - 31/07/2020)

(DFG Priority Programme (SPP) 2037 - Scalable Data Management for Future Hardware):
ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis
Prof. Dr.-Ing. Klaus Meyer-Wegener; Dr.-Ing. Stefan Wildermann; Prof. Dr.-Ing. Jürgen Teich
(28/08/2017 - 31/08/2020)

AConFPGA: Approximate Computing on FPGAs
Prof. Dr.-Ing. Jürgen Teich
(13/03/2017)

(TRR 89: Invasive Computing):
TCPA_INT: Integration and Coupling of Tightly Coupled Processor Arrays (T01)
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01/03/2017 - 29/02/2020)

AdaptAC: Adaptive Approximate Computing in FPGA-basierter Bildverarbeitung
Prof. Dr.-Ing. Jürgen Teich
(24/08/2016 - 31/12/2017)


Project member

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HighPerMeshes: Domänenspezifische Programmierung und zielplattformbewusste Compiler-Infrastruktur für Algorithmen auf unstrukturierten Gittern
PD Dr.-Ing. Frank Hannig
(01/04/2017 - 31/03/2020)

SSI: Sustainable Smart Industry
Prof. Dr. Kai-Ingo Voigt
(01/01/2017 - 31/12/2019)

ESI 2: ESI-Anwendungszentrum für die digitale Automatisierung, den digitalen Sport und die Automobilsensorik der Zukunft
Prof. Dr.-Ing. Jürgen Teich
(01/01/2015 - 31/12/2018)

(SPP 1648: Software for Exascale Computing):
ExaStencils: ExaStencils - Advanced Stencil-Code Engineering
PD Dr.-Ing. Frank Hannig; Prof. Dr. Harald Köstler; Prof. Dr. Ulrich Rüde; Prof. Dr.-Ing. Jürgen Teich
(01/01/2013 - 31/12/2018)

RTG 1773: Heterogeneous Image Systems
Prof. Dr. Marc Stamminger
(01/10/2012 - 31/03/2017)


Publications (Download BibTeX)

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Teich, J. (1993). A Compiler for Application-Specific Processor Arrays (Zugl. Doktorarbeit) (Dissertation).
Teich, J., Thiele, L., & Zhang, L. (1993). Minimal communication in massively parallel architectures. In Proc. of PARS Workshop 93 (pp. 154-161). Dresden, Germany,.
Teich, J., & Thiele, L. (1993). Partitioning of processor arrays: A piecewise regular approach. Integration-The Vlsi Journal, 14(3):297-332. https://dx.doi.org/10.1016/0167-9260(93)90013-3
Teich, J., & Thiele, L. (1992). A transformative approach to the partitioning of processor arrays. In Proc. Int. Conf. on Application Specific Array Processors (pp. 4-20). Berkeley, CA, U.S.A.,.
Teich, J., & Thiele, L. (1992). Control generation in the design of processor array. In Parallel Processing on VLSI Arrays Kluwer Academic Publishers.
Arzt, U., Teich, J., Schumacher, M., & Thiele, L. (1992). Hierarchical concepts in the design of processor arrays. In Proc. CompEuro 1992 (pp. 232-237). The Hague, The Netherlands,.
Arzt, U., Teich, J., & Thiele, L. (1992). The concepts of COMPAR: A compiler for massive parallel architectures. In Proc. International Symposium on Circuits and Systems (pp. 681-684). San Diego, CA, U.S.A.,.
Teich, J., & Thiele, L. (1991). Control generation in the design of processor arrays. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 3(1-2), 77-92. https://dx.doi.org/10.1007/BF00927836
Teich, J., & Thiele, L. (1991). Uniform design of parallel programs for DSP. In In Proc. IEEE Int. Symp. Circuits and Systems (ISCAS) (pp. 344a-347a). Singapore.
Huber, M., Teich, J., & Thiele, L. (1990). Design of configurable processor arrays. In Proc. IEEE Int. Symp. Circuits and Systems (pp. 970-973).

Last updated on 2017-18-04 at 15:02