Prof. Dr.-Ing. Jürgen Teich


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Awards / Honours

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2018 : Mitgliedschaft acatech - Deutsche Akademie der Technikwissenschaften
2016 : HiPEAC Paper Award: Formal Reliability Analysis of Switched Ethernet Automotive Networks under Transient Transmission Errors
2015 : Best Paper Award: Reliability of Space-Grade vs. COTS SRAM-based FPGA in N-Modular Redundancy
2015 : HiPEAC Paper Award: Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures
2014 : Best Paper Award: Automatic Graph-based Success Tree Construction and Analysis

Project lead

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Prof. Dr.-Ing. Jürgen Teich
(01/08/2018 - 31/07/2020)

(DFG Priority Programme (SPP) 2037 - Scalable Data Management for Future Hardware):
ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis
Prof. Dr.-Ing. Klaus Meyer-Wegener; Dr.-Ing. Stefan Wildermann; Prof. Dr.-Ing. Jürgen Teich
(28/08/2017 - 31/08/2020)

AConFPGA: Approximate Computing on FPGAs
Prof. Dr.-Ing. Jürgen Teich

(TRR 89: Invasive Computing):
TCPA_INT: Integration and Coupling of Tightly Coupled Processor Arrays (T01)
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01/03/2017 - 29/02/2020)

AdaptAC: Adaptive Approximate Computing in FPGA-basierter Bildverarbeitung
Prof. Dr.-Ing. Jürgen Teich
(24/08/2016 - 31/12/2017)

Project member

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HighPerMeshes: Domänenspezifische Programmierung und zielplattformbewusste Compiler-Infrastruktur für Algorithmen auf unstrukturierten Gittern
PD Dr.-Ing. Frank Hannig
(01/04/2017 - 31/03/2020)

SSI: Sustainable Smart Industry
Prof. Dr. Kai-Ingo Voigt
(01/01/2017 - 31/12/2019)

ESI 2: ESI-Anwendungszentrum für die digitale Automatisierung, den digitalen Sport und die Automobilsensorik der Zukunft
Prof. Dr.-Ing. Jürgen Teich
(01/01/2015 - 31/12/2018)

(SPP 1648: Software for Exascale Computing):
ExaStencils: ExaStencils - Advanced Stencil-Code Engineering
PD Dr.-Ing. Frank Hannig; Prof. Dr. Harald Köstler; Prof. Dr. Ulrich Rüde; Prof. Dr.-Ing. Jürgen Teich
(01/01/2013 - 31/12/2018)

RTG 1773: Heterogeneous Image Systems
Prof. Dr. Marc Stamminger
(01/10/2012 - 31/03/2017)

Publications (Download BibTeX)

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Pourmohseni, B., Wildermann, S., Glaß, M., & Teich, J. (2019). Hard Real-Time Application Mapping Reconfiguration for NoC-Based Many-Core Systems. Real-Time Systems, 1-37.
Smirnov, F., Pourmohseni, B., Glaß, M., & Teich, J. (2019). IGOR, get me the Optimum! Prioritizing Important Design Decisions During the DSE of Embedded Systems. In Proceedings of the CODES+ISSS: International Conference on Hardware/Software Codesign and System Synthesis. New York, NY, US.
Becher, A., & Teich, J. (2019). In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing. In Proceedings of the 15th International Workshop on Data Management on New Hardware (DaMoN) Held with ACM SIGMOD/PODS 2019. Amsterdam, NL.
Pourmohseni, B., Smirnov, F., Wildermann, S., & Teich, J. (2019). Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. In Proceedings of the 31th Euromicro Conference on Real-Time Systems (ECRTS) (pp. 12:1--12:24). Stuttgart, Germany.
Roloff, S., Hannig, F., & Teich, J. (2019). Modeling and Simulation of Invasive Applications and Architectures. Singapore: Springer.
Letras, M., Falk, J., Schwarzer, T., & Teich, J. (2019). On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures. In Proceedings of the 22st International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019, Sankt Goar, Germany (pp. 1-9). Sankt Goar, Germany, DE: ACM.
Ah Sue, J., Brand, P., Falk, J., Hasholzner, R., & Teich, J. (2019). Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and its Application to Cellular Modems (to appear). In HCII 2019 Late Breaking Work Papers Proceedings (pp. 1-12). Orlando, Florida, USA, US: New York, NY, USA: Springer.
Nisar, A., Ah Sue, J., & Teich, J. (2019). Performance Comparison between Machine Learning based LTE Downlink Grant Predictors. In Proceedings of the 21st International Conference on Artificial Intelligence. Las Vegas, US.
Witterauf, M., Hannig, F., & Teich, J. (2019). Polyhedral Fragments: An Efficient Representation for Symbolically Generating Code for Processor Arrays. In Proceedings of the International Conference on Formal Methods and Models for System Design (MEMOCODE). San Diego.
Brand, M., Witterauf, M., Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2019). *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing. Concurrency and Computation-Practice & Experience.

Last updated on 2019-16-08 at 10:01