Prof. Dr.-Ing. Jürgen Teich



Organisation


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lehrstuhl für Informatik 1 (IT-Sicherheitsinfrastrukturen)


Awards / Honours

Go to first page Go to previous page 1 of 3 Go to next page Go to last page

2018 : Mitgliedschaft acatech - Deutsche Akademie der Technikwissenschaften
2016 : HiPEAC Paper Award: Formal Reliability Analysis of Switched Ethernet Automotive Networks under Transient Transmission Errors
2015 : Best Paper Award: Reliability of Space-Grade vs. COTS SRAM-based FPGA in N-Modular Redundancy
2015 : HiPEAC Paper Award: Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures
2014 : Best Paper Award: Automatic Graph-based Success Tree Construction and Analysis



Project lead

Go to first page Go to previous page 1 of 10 Go to next page Go to last page

SHARE: SHARE at FAU
Prof. Dr.-Ing. Jürgen Teich
(01/08/2018 - 31/07/2020)

(DFG Priority Programme (SPP) 2037 - Scalable Data Management for Future Hardware):
ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis
Prof. Dr.-Ing. Klaus Meyer-Wegener; Dr.-Ing. Stefan Wildermann; Prof. Dr.-Ing. Jürgen Teich
(28/08/2017 - 31/08/2020)

AConFPGA: Approximate Computing on FPGAs
Prof. Dr.-Ing. Jürgen Teich
(13/03/2017)

(TRR 89: Invasive Computing):
TCPA_INT: Integration and Coupling of Tightly Coupled Processor Arrays (T01)
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01/03/2017 - 29/02/2020)

AdaptAC: Adaptive Approximate Computing in FPGA-basierter Bildverarbeitung
Prof. Dr.-Ing. Jürgen Teich
(24/08/2016 - 31/12/2017)


Project member

Go to first page Go to previous page 1 of 2 Go to next page Go to last page

HighPerMeshes: Domänenspezifische Programmierung und zielplattformbewusste Compiler-Infrastruktur für Algorithmen auf unstrukturierten Gittern
PD Dr.-Ing. Frank Hannig
(01/04/2017 - 31/03/2020)

SSI: Sustainable Smart Industry
Prof. Dr. Kai-Ingo Voigt
(01/01/2017 - 31/12/2019)

ESI 2: ESI-Anwendungszentrum für die digitale Automatisierung, den digitalen Sport und die Automobilsensorik der Zukunft
Prof. Dr.-Ing. Jürgen Teich
(01/01/2015 - 31/12/2018)

(SPP 1648: Software for Exascale Computing):
ExaStencils: ExaStencils - Advanced Stencil-Code Engineering
PD Dr.-Ing. Frank Hannig; Prof. Dr. Harald Köstler; Prof. Dr. Ulrich Rüde; Prof. Dr.-Ing. Jürgen Teich
(01/01/2013 - 31/12/2018)

RTG 1773: Heterogeneous Image Systems
Prof. Dr. Marc Stamminger
(01/10/2012 - 31/03/2017)


Publications (Download BibTeX)

Go to first page Go to previous page 2 of 72 Go to next page Go to last page

Letras, M., Falk, J., Schwarzer, T., & Teich, J. (2019). On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures. In Proceedings of the 22st International Workshop on Software and Compilers for Embedded Systems, SCOPES 2019, Sankt Goar, Germany (pp. 1-9). Sankt Goar, Germany, DE: ACM.
Ah Sue, J., Brand, P., Falk, J., Hasholzner, R., & Teich, J. (2019). Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and its Application to Cellular Modems (to appear). In HCII 2019 Late Breaking Work Papers Proceedings (pp. 1-12). Walt Disney World Swan and Dolphin Resort, Orlando, Florida, USA, US: New York, NY, USA: Springer.
Nisar, A., Ah Sue, J., & Teich, J. (2019). Performance Comparison between Machine Learning based LTE Downlink Grant Predictors. In Proceedings of the 21st International Conference on Artificial Intelligence. Las Vegas, US.
Brand, M., Witterauf, M., Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2019). *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing. Concurrency and Computation-Practice & Experience. https://dx.doi.org/10.1002/cpe.5149
Becher, A., Herrmann, A., Wildermann, S., & Teich, J. (2019). ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. In Gesellschaft für Informatik, Bonn (Eds.), Proceedings of the 1st Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) (pp. 51-70). Universität Rostock, DE: Bonn: Gesellschaft für Informatik.
Groth, S., Schmitt, C., Teich, J., & Hannig, F. (2019). SYCL Code Generation for Multigrid Methods. In Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES) (pp. 41-44). Sankt Goar, DE: ACM.
Özkan, M.A., Reiche, O., Qiao, B., Membarth, R., Teich, J., & Hannig, F. (2019). Synthesizing High-Performance Image Processing Applications with Hipacc. In Proceedings of the Demo at the University Booth at Design, Automation and Test in Europe (DATE). Florence, IT.
Smirnov, F., Pourmohseni, B., Glaß, M., & Teich, J. (2019). Variety-Aware Routing Encoding for Efficient Design Space Exploration of Automotive Communication Networks. In Proceedings of the 5th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS). Heraklion, Kreta, GR.
Echavarria Gutiérrez, J.A., Wildermann, S., & Teich, J. (2018). AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. In Proceedings of 2018 International Conference on Field Programmable Technology. Naha, Okinawa, JP.
Weichslgartner, A., Wildermann, S., Gangadharan, D., Glaß, M., & Teich, J. (2018). A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. ACM Transactions on Embedded Computing Systems.

Last updated on 2017-18-04 at 15:02