Hager G, Deserno F, Wellein G (2003)
Publication Type: Conference contribution
Publication year: 2003
Publisher: Springer-Verlag
City/Town: New York, LLC
Pages Range: 425-442
Conference Proceedings Title: High Performance Computing in Science and Engineering, Munich 2002: Transactions of the First Joint HLRB and KONWIHR Status and Result Workshop, October 10-11, Technical University of Munich, Germany.
Event location: München
ISBN: 3540004742
APA:
Hager, G., Deserno, F., & Wellein, G. (2003). Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture. In High Performance Computing in Science and Engineering, Munich 2002: Transactions of the First Joint HLRB and KONWIHR Status and Result Workshop, October 10-11, Technical University of Munich, Germany. (pp. 425-442). München: New York, LLC: Springer-Verlag.
MLA:
Hager, Georg, Frank Deserno, and Gerhard Wellein. "Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture." Proceedings of the High Performance Computing in Science and Engineering, München New York, LLC: Springer-Verlag, 2003. 425-442.
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