Jung M, Ferizi A, Weigel R (2010)
Publication Type: Conference contribution
Publication year: 2010
Publisher: IEEE
Pages Range: 2291-2294
Conference Proceedings Title: Asia Pacific Microwave Conference
Event location: Yokohama
ISBN: 978-1-4244-7590-2
URI: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5728318
Today, most of the locating systems are based on phase-locked loop (PLL) architectures for synthesizers. The synthesizer as a key element for location accuracy needs a chargepump with an exact current matching for improved phase noise performance. Especially in indoor scenarios, where sensor nodes must reach a precision below a few centimeters, the fidelity of the synthesizer system is important. This paper addresses the design of a chargepump with enhanced current matching and reduced clock-feedthrough in a FMCW based sensor node. The difference between a conventional chargepump design and the enhanced design is presented and compared to show the current matching improvement and clock-feedthrough reduction. The different designs were manufactured in a 0.13μm CMOS process by IBM. They are running in a PLL with 128MHz reference frequency and have an output current of 100μA with a total power consumption of 1mW for the chargepump with phase-frequency detector (PFD).
APA:
Jung, M., Ferizi, A., & Weigel, R. (2010). A Chargepump with enhanced Current Matching and reduced Clock-Feedthrough in Wireless Sensor Nodes. In Asia Pacific Microwave Conference (pp. 2291-2294). Yokohama: IEEE.
MLA:
Jung, Melanie, Alban Ferizi, and Robert Weigel. "A Chargepump with enhanced Current Matching and reduced Clock-Feedthrough in Wireless Sensor Nodes." Proceedings of the Asia Pacific Microwave Conference, Yokohama IEEE, 2010. 2291-2294.
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