A Chargepump with enhanced Current Matching and reduced Clock-Feedthrough in Wireless Sensor Nodes - Jung, Melanie; Ferizi, Alban; Weigel, Robert (Asia Pacific Microwave Conference, 2010)
Today, most of the locating systems are based on phase-locked loop (PLL) architectures for synthesizers. The synthesizer as a key element for location accuracy needs a chargepump with an exact current matching for improved phase noise performance. Especially in indoor scenarios, where sensor nodes must reach a precision below a few centimeters, the fidelity of the synthesizer system is important. This paper addresses the design of a chargepump with enhanced current matching and reduced clock-feedthrough in a FMCW based sensor node. The difference between a conventional chargepump design and the enhanced design is presented and compared to show the current matching improvement and clock-feedthrough reduction. The different designs were manufactured in a 0.13μm CMOS process by IBM. They are running in a PLL with 128MHz reference frequency and have an output current of 100μA with a total power consumption of 1mW for the chargepump with phase-frequency detector (PFD).
elib2cris::1512001600,jung2010a
Keywords: Clocks; Phase frequency detector; Phase locked loops; Transconductance; Transistors; Wireless communication; Wireless sensor networks