An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors

Hofmann J, Hager G, Wellein G, Fey D (2017)

Publication Type: Conference contribution

Publication year: 2017

Publisher: Springer

Series: Lecture Notes in Computer Science

City/Town: Cham

Conference Proceedings Title: High Performance Computing. ISC 2017. Lecture Notes in Computer Science, vol 10266

Event location: Frankfurt

ISBN: 978-3-319-58667-0

DOI: 10.1007/978-3-319-58667-0_16

Authors with CRIS profile

Johannes Hofmann Lehrstuhl für Informatik 3 (Rechnerarchitektur) Georg Hager Regionales Rechenzentrum Erlangen (RRZE) Gerhard Wellein Professur für Höchstleistungsrechnen Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

How to cite

APA:

Hofmann, J., Hager, G., Wellein, G., & Fey, D. (2017). An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors. In High Performance Computing. ISC 2017. Lecture Notes in Computer Science, vol 10266. Frankfurt: Cham: Springer.

MLA:

Hofmann, Johannes, et al. "An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors." Proceedings of the 32nd International Conference on High Performance Computing: ISC High Performance 2017, Frankfurt Cham: Springer, 2017.

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