Growth and Curvature Modelling of GaN-on-Si(111) for Vertical Power Devices
Internally funded project
Start date : 01.09.2021
Project details
Short description
Das Forschungsprojekt wird im Rahmen
eines LEB-Promotionsvorhabens in Zusammenarbeit mit externen
Kooperationspartnern bearbeitet.
High-power
switching devices play a key role in applications such as data centres,
vehicles and power plants. The main goal in developing novel power
devices is to improve the efficiency and reliability of the switching
device while keeping costs low. The interest in developing GaN-based
power devices stems from the fact that it has improved material
properties, i.e., saturation velocity, electron mobility and critical
electric field, than SiC and Si. Consequently, power switching devices
based on GaN can offer low on-resistance, high breakdown voltage and
fast switching.
Growing high quality GaN on Si(111) remains challenging due to high lattice and thermal mismatch leading to high threading dislocation density, severe curvature and cracks on the wafers. Therefore, the stress management in these structures must be fully understood.
In this work, GaN-based structures that can withstand high breakdown voltage while exhibiting low on-resistance are fabricated by metal-organic chemical vapour deposition. The wafers are then delivered to the partners of the YESvGaN project (European funded project) for processing and testing. Further, a curvature model is being developed to predict the wafer shape during growth and after cooling based on the epitaxy process to provide more information on stress management.
Growing high quality GaN on Si(111) remains challenging due to high lattice and thermal mismatch leading to high threading dislocation density, severe curvature and cracks on the wafers. Therefore, the stress management in these structures must be fully understood.
In this work, GaN-based structures that can withstand high breakdown voltage while exhibiting low on-resistance are fabricated by metal-organic chemical vapour deposition. The wafers are then delivered to the partners of the YESvGaN project (European funded project) for processing and testing. Further, a curvature model is being developed to predict the wafer shape during growth and after cooling based on the epitaxy process to provide more information on stress management.
Scientific Abstract
Vertical power devices based on GaN-on-Si(111) potentially offer several advantages over their lateral counterpart, i.a., superior thermal management, higher reliability, and the capability of achieving high breakdown voltage and current density without increasing the chip size [1]. In addition, Si is attractive, due to the large diameter availability, low cost and good thermal conductivity compared to other substrates. However, for device operation at high voltage (> 1 kV), several micrometers of high quality GaN must be deposited. This is a major challenge as lattice and thermal mismatch lead to severe wafer curvature and eventually cracks if not properly controlled. Further, a wafer bow < ±50 µm is required for processing in a conventional CMOS line [2]. In case of substrate diameters beyond the state of the art this issue becomes even more critical, since the bow typically increases with the square of the wafer diameter. Recently the market trend for GaN-on-Si(111) is moving from 150 mm to 200 mm and development towards 300 mm is visible. Thus, a further optimized epitaxy and a model to predict the wafer bow is essential.
The target of this thesis is to provide GaN-on-Si(111) epi-stacks grown on 8” substrates which have the desired properties to fabricate power transistors with a breakdown voltage of ~1200V and a specific on-resistance of < 4 mΩ cm2. In addition, a curvature model will be developed to predict the curvature evolution during growth and after cooling based on the epitaxy process.
[1] Y. Zhang, M. Sun, Z. Liu, D. Piedra, H. Lee, F. Gao, T. Fujishima, T. Palacios, IEEE Trans. Electron Devices, 60, 2224–2230 (2013).
[2] M. Ishida, T. Ueda, T. Tanaka, D. Ueda, IEEE Trans. Electron Devices, 60, 3053–3059 (2013).
