Dedizierte massiv parallele Systeme (PARO)

PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications (2008) Hannig F, Ruckdeschel H, Dutta H, Teich J Conference contribution Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures (2008) Wolinski C, Kuchcinski K, Teich J, Hannig F Conference contribution Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures (2008) Wolinski C, Kuchcinski K, Teich J, Hannig F Conference contribution Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures (2008) Wolinski C, Kuchcinski K, Teich J, Hannig F Conference contribution Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays (2007) Dutta H, Hannig F, Ruckdeschel H, Teich J Journal article A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation (2007) Teich J, Hannig F, Ruckdeschel H, Dutta H, Kissler D, Stravet A Conference contribution Massively Parallel Processor Architectures: A Co-design Approach (2007) Dutta H, Hannig F, Kupriyanov O, Kissler D, Teich J, Schaffer R, Siegel S, et al. Conference contribution A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms (2006) Dutta H, Hannig F, Teich J Other publication type Controller Synthesis for Mapping Partitioned Programs on Array Architectures (2006) Dutta H, Hannig F, Teich J Conference contribution Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints (2006) Dutta H, Hannig F, Teich J Conference contribution