Prof. Dr. Joachim Neves Rodrigues

Lehrstuhl für System-on-Chip

A receiver architecture for devices in wireless body area networks (2012) Sjöland H, Anderson JB, Bryant C, Chandra R, Edfors O, Johansson AJ, Mazloum NS, et al. Journal article IR-drop reduction in sub-VT circuits by de-synchronization (2012) Karlsson A, Andersson O, Sparso J, Rodrigues JN Conference contribution A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS (2012) Sherazi MY, Nilsson P, Sjoland H, Rodrigues JN Conference contribution Sizing of dual-VT gates for sub-VT circuits (2012) Mohammadi B, Sherazi SM, Rodrigues JN Conference contribution Sub-VT design of a wake-up receiver back-end in 65 nm CMOS (2012) Mazloum NS, Rodrigues JN, Edfors O Conference contribution A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS (2012) Meinerzhagen P, Andersson O, Mohammadi B, Sherazi Y, Burg A, Rodrigues JN Conference contribution Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology (2011) Meinerzhagen P, Sherazi SM, Burg A, Rodrigues JN Journal article Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection (2011) Akgun OC, Rodrigues JN, SparsØ J Journal article Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping (2011) Zhang C, Diaz I, Andersson P, Rodrigues JN, Öwall V Conference contribution Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain (2011) Sherazi SM, Nilsson P, Akgun OC, Sjoland H, Rodrigues JN Conference contribution