A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS

Sherazi MY, Nilsson P, Sjoland H, Rodrigues JN (2012)

Publication Type: Conference contribution

Publication year: 2012

Pages Range: 448-451

Conference Proceedings Title: 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

Event location: ESP

ISBN: 9781467312615

DOI: 10.1109/ICECS.2012.6463654

Abstract

Measurements of a sub-threshold (sub-VT) decimation filter, composed of four half band digital (HBD) filters in 65 nm CMOS are presented. Different unfolded architectures are analyzed and implemented to combat speed degradation. The architectures are analyzed for throughput and energy efficiency over several threshold options. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The simulation results are validated by measurements and demonstrate that low-power standard threshold logic (LP-SVT) and different architectural flavours are suitable for a low-power implementation. Silicon measurements prove functionality down to 350mV supply, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle. © 2012 IEEE.

Authors with CRIS profile

Joachim Neves Rodrigues

Involved external institutions

Lund University / Lunds universitet SE Sweden (SE)

How to cite

APA:

Sherazi, M.Y., Nilsson, P., Sjoland, H., & Rodrigues, J.N. (2012). A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS. In 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 (pp. 448-451). ESP.

MLA:

Sherazi, M. Yasser, et al. "A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS." Proceedings of the 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, ESP 2012. 448-451.

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