Vahid Lari

Sonderforschungsbereich/Transregio 89 Invasives Rechnen Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores (2017) Khdr H, Pagani S, Rodrigues Sousa E, Lari V, Pathania A, Hannig F, Shafique M, et al. Journal article LoopInvader: A Compiler for Tightly Coupled Processor Arrays (2016) Tanase AP, Witterauf M, Sousa É, Lari V, Hannig F, Teich J Conference contribution Providing Fault Tolerance Through Invasive Computing (2016) Lari V, Weichslgartner A, Tanase AP, Witterauf M, Khosravi F, Teich J, Heißwolf J, et al. Journal article Invasive Tightly Coupled Processor Arrays (2016) Lari V Book chapter / Article in edited volumes Invasive Tightly Coupled Processor Arrays (2015) Lari V Thesis Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays (2015) Teich J, Boppu S, Hannig F, Lari V Book chapter / Article in edited volumes Adaptive fault tolerance through invasive computing (2015) Witterauf M, Tanase AP, Teich J, Lari V, Zwinkau A, Snelting G Conference contribution, Conference Contribution A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays (2015) Lari V, Tanase AP, Teich J, Witterauf M, Khosravi F, Hannig F, Meyer B Conference contribution, Conference Contribution Techniques for on-demand structural redundancy for massively parallel processor arrays (2015) Teich J, Lari V, Tanase AP, Witterauf M, Khosravi F, Meyer B Journal article, Original article On-demand fault-tolerant loop processing on massively parallel processor arrays (2015) Tanase AP, Witterauf M, Teich J, Hannig F, Lari V Conference contribution, Conference Contribution