Jorge Alfonso Echavarria Gutiérrez

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

IP-Cores Watermarking Scheme at Behavioral Level Using Genetic Algorithms (2019) Echavarria Gutiérrez JA, Morales-Reyes A, Cumplido R, Salido MÁ, Feregrino C Journal article, Original article Can Approximate Computing Reduce Power Consumption on FPGAs? (2018) Echavarria Gutiérrez JA, Schütz K, Becher A, Wildermann S, Teich J Conference contribution, Original article AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs (2018) Echavarria Gutiérrez JA, Wildermann S, Teich J Conference contribution, Original article Design Space Exploration of Multi-output Logic Function Approximations (2018) Echavarria Gutiérrez JA, Wildermann S, Teich J Conference contribution, Original article Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs (2018) Echavarria Gutiérrez JA, Schütz K, Becher A, Wildermann S, Teich J Conference contribution, Original article Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders (2017) Echavarria Gutiérrez JA, Wildermann S, Potwigin E, Teich J Journal article, Original article Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics (2017) Pirkl J, Becher A, Echavarria Gutiérrez JA, Teich J, Wildermann S Conference contribution FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs (2016) Echavarria Gutiérrez JA, Wildermann S, Becher A, Teich J, Ziener D Conference contribution, Original article A LUT-Based Approximate Adder (2016) Becher A, Echavarria Gutiérrez JA, Ziener D, Wildermann S, Teich J Conference contribution Approximate Adder Structures on FPGAs (2015) Becher A, Echavarria Gutiérrez JA, Ziener D, Teich J Conference contribution