Prof. Dr.-Ing. Dietmar Fey

Lehrstuhl für Informatik 3 (Rechnerarchitektur)

TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms (2021) Hosseinzadeh S, Biglari M, Fey D Journal article A Case for Function-As-A-Service with Disaggregated FPGAs (2021) Ringlein B, Abel F, Diamantopoulos D, Weiss B, Hagleitner C, Reichenbach M, Fey D Conference contribution Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles (2021) Prabahar JR, Fey D Conference contribution RISC-V3: A RISC-V Compatible CPU with a Data Path Based on Redundant Number Systems (2021) Reichenbach M, Knödtel J, Rachuj S, Fey D Journal article Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic (2021) Fey D, Reuben JR, Slesazeck S Conference contribution Simulating large neural networks embedding MLC RRAM as weight storage considering device variations (2021) Fritscher M, Knödtel J, Reiser D, Mallah M, Pechmann S, Fey D, Reichenbach M Conference contribution, Original article Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design (2021) Vaas S, Ulbrich P, Eichler C, Wägemann P, Reichenbach M, Fey D Conference contribution, Conference Contribution Programming Reconfigurable Heterogeneous Computing Clusters Using MPI with Transpilation (2020) Ringlein B, Abel F, Ditter A, Weiss B, Hagleitner C, Fey D Conference contribution A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories (2020) Knödtel J, Fritscher M, Reiser D, Fey D, Breiling M, Reichenbach M Conference contribution, Conference Contribution Direct state transfer in MLC based memristive ReRAM devices for ternary computing (2020) Fey D, Reuben JR Conference contribution