Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Transparent FPGA Acceleration with TensorFlow (2021) Pfenning S, Holzinger P, Reichenbach M Conference contribution, Conference Contribution Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates (2021) Reuben JR, Pechmann S Journal article Fast HBM Access with FPGAs: Analysis, Architectures, and Applications (2021) Holzinger P, Reiser D, Hahn T, Reichenbach M Conference contribution, Conference Contribution Programming Reconfigurable Heterogeneous Computing Clusters Using MPI with Transpilation (2020) Ringlein B, Abel F, Ditter A, Weiss B, Hagleitner C, Fey D Conference contribution A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories (2020) Knödtel J, Fritscher M, Reiser D, Fey D, Breiling M, Reichenbach M Conference contribution, Conference Contribution Direct state transfer in MLC based memristive ReRAM devices for ternary computing (2020) Fey D, Reuben JR Conference contribution Rediscovering majority logic in the post-CMOS era: A perspective from in-memory computing (2020) Reuben JR Journal article Impact of Performance Estimation on Fast Processor Simulators (2020) Rachuj S, Fey D, Reichenbach M Conference contribution, Conference Contribution Disjoint Sum of Products by Orthogonalizing Difference-Building circle minus (2020) Can Y, Yaz O, Fey D Journal article A parallel-friendly majority gate to accelerate in-memory computation (2020) Reuben JR, Pechmann S Conference contribution