Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines (2009) Dutta H, Zhai J, Hannig F, Teich J Conference contribution Modeling and Simulation of IEEE 802.11g using OMNeT++ (2009) Sarkar N, Membarth R Book chapter / Article in edited volumes System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance (2009) Lari V, Hannig F, Teich J Conference contribution Self-Organizing Multi-cue Fusion for FPGA-based Embedded Imaging (2009) Wildermann S, Walla G, Ziermann T, Teich J Conference contribution Self-Organizing Bandwidth Sharing in Priority-based Medium Access (2009) Wildermann S, Ziermann T, Teich J Conference contribution Run time Mapping of AdaptiveApplications onto Homogeneous NoC-based Reconfigurable Architectures (2009) Wildermann S, Ziermann T, Teich J Conference contribution Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning (2009) Hannig F, Dutta H, Teich J Conference contribution Optimization Flow for Algorithm Mapping on Graphics Cards (2009) Membarth R, Hannig F, Dutta H, Teich J Conference contribution Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators (2009) Sim JE, Wong WF, Teich J Conference contribution Minimizing Internal Fragmentation by Fine-grained Two-dimensional Module Placement for Runtime Reconfigurable Systems (2009) Koch D, Beckhoff C, Teich J Conference contribution