Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Impact of loop tiling on the controller logic of acceleration engines (2009) Dutta H, Zhai J, Hannig F, Teich J Conference contribution, Conference Contribution CODES+ISSS 2007 guest editors' introduction (2009) Dutt N, Teich J Journal article, Editorial SYSTEMCODESIGNER - An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications (2009) Keinert J, Streubühr M, Schlichter T, Falk J, Gladigau J, Teich J, Haubelt C, Meredith M Journal article, Original article Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures (2009) Kissler D, Strawetz A, Hannig F, Teich J Journal article Electronic System-Level Synthesis Methodologies (2009) Gerstlauer A, Haubelt C, Pimentel A, Stefanov T, Gajski D, Teich J Journal article A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors (2009) Dutta H, Kissler D, Hannig F, Kupriyanov O, Teich J, Pottier B Journal article Data Flow Based System Level Modeling, Analysis, and Synthesis of High-Performance Streaming Image Processing Applications (2009) Keinert J Thesis Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis (2009) Dutta H, Hannig F, Teich J Conference contribution Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines (2009) Dutta H, Zhai J, Hannig F, Teich J Conference contribution Modeling and Simulation of IEEE 802.11g using OMNeT++ (2009) Sarkar N, Membarth R Book chapter / Article in edited volumes