Reuben JR (2020)
Publication Type: Journal article
Publication year: 2020
Book Volume: 11
Article Number: 496
Journal Issue: 5
DOI: 10.3390/MI11050496
The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the 'von Neumann bottleneck' or 'memory wall'. Emerging resistance switching memories (memristors) show promising signs to overcome the 'memory wall' by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory READ operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory READ and WRITE operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T-1R array, which is faster than IMPLY, NAND, NOR and other similar logic primitives.
APA:
Reuben, J.R. (2020). Binary addition in resistance switching memory array by sensing majority. Micromachines, 11(5). https://dx.doi.org/10.3390/MI11050496
MLA:
Reuben, John Reuben. "Binary addition in resistance switching memory array by sensing majority." Micromachines 11.5 (2020).
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