Hager G, Zeiser T, Wellein G (2008)
Publication Language: English
Publication Type: Conference contribution
Publication year: 2008
Publisher: CFP08023-CDR
Edited Volumes: IPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM
City/Town: IEEE Catalog Number
Pages Range: 1-7
Conference Proceedings Title: Proceedings of the 2008 IEEE International Parallel & Distributed Processing Symposium
Event location: Miami, FL, USA
ISBN: 978-1-4244-1693-6
DOI: 10.1109/IPDPS.2008.4536341
Processor and system architectures that feature multiple memory controllers are prone to show bottlenecks and erratic performance numbers on codes with regular access patterns. Although such effects are well known in the form of cache thrashing and aliasing conflicts, they become more severe when memory access is involved. Using the new Sun UltraSPARC T2 processor as a prototypical multi-core design, we analyze performance patterns in low-level and application benchmarks and show ways to circumvent bottlenecks by careful data layout and padding. ©2008 IEEE.
APA:
Hager, G., Zeiser, T., & Wellein, G. (2008). Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers. In Proceedings of the 2008 IEEE International Parallel & Distributed Processing Symposium (pp. 1-7). Miami, FL, USA: IEEE Catalog Number: CFP08023-CDR.
MLA:
Hager, Georg, Thomas Zeiser, and Gerhard Wellein. "Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers." Proceedings of the IEEE International Symposium on Parallel and Distributed Processing, 2008. IPDPS 2008, Miami, FL, USA IEEE Catalog Number: CFP08023-CDR, 2008. 1-7.
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