Resource-awareness on heterogeneous MPSoCs for image processing

Beitrag in einer Fachzeitschrift

Details zur Publikation

Autorinnen und Autoren: Paul J, Stechele W, Oechslein B, Erhardt CP, Schedel J, Lohmann D, Schröder-Preikschat W, Kröhnert M, Asfour T, Sousa É, Hannig F, Lari V, Teich J, Grudnitsky A, Bauer L, Henkel J
Zeitschrift: Journal of Systems Architecture
Verlag: Elsevier
Jahr der Veröffentlichung: 2015
Band: 61
Heftnummer: 10
Seitenbereich: 668-680
ISSN: 1383-7621


Multiprocessor system-on-chip (MPSoC) designs offer a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. On-chip MPPAs can be used to accelerate low-level image-processing algorithms with massive inherent parallelism. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, among others. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to under-utilization of some type of PEs while overloading others. In this work, we investigate the benefits of using a heterogeneous MPSoC for accelerating various stages within a real-world image-processing algorithm for object-recognition. A case study demonstrates that a resource-aware programming model called Invasive Computing helps to improve the throughput and worst observed latency of the application program, by dynamically mapping applications to different types of PEs available on a heterogeneous MPSoC.

FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Erhardt, Christoph Paul
Sonderforschungsbereich/Transregio 89 Invasives Rechnen
Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lari, Vahid
Sonderforschungsbereich/Transregio 89 Invasives Rechnen
Lohmann, Daniel PD Dr.
Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme)
Oechslein, Benjamin
Sonderforschungsbereich/Transregio 89 Invasives Rechnen
Schedel, Jens Dr.
Sonderforschungsbereich/Transregio 89 Invasives Rechnen
Schröder-Preikschat, Wolfgang Prof. Dr.-Ing.
Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme)
Rodrigues Sousa, Éricles
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Einrichtungen weiterer Autorinnen und Autoren

Karlsruhe Institute of Technology (KIT)
Technische Universität München (TUM)


Architecture and Compiler Design
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Paul, J., Stechele, W., Oechslein, B., Erhardt, C.P., Schedel, J., Lohmann, D.,... Henkel, J. (2015). Resource-awareness on heterogeneous MPSoCs for image processing. Journal of Systems Architecture, 61(10), 668-680.

Paul, Johny, et al. "Resource-awareness on heterogeneous MPSoCs for image processing." Journal of Systems Architecture 61.10 (2015): 668-680.


Zuletzt aktualisiert 2019-24-08 um 07:13