SiC Power Module Loss Reduction by PWM Gate Drive Patterns and Impedance-Optimized Gate Drive Voltages

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Details zur Publikation

Autor(en): März M, Gerstner H, Heckel T, Endruschat A, Rosskopf A, Eckardt B
Jahr der Veröffentlichung: 2017
Sprache: Englisch


Abstract


This paper presents a novel procedure to determine the internal gate-source voltage inside a multi-chip power module using the example of a SiC half bridge module. Based on the lumped elements of the gate circuit calculated by a quasi-static electromagnetic simulation, each field-effect transistor is represented by a single, voltage dependent capacitor. The procedure is validated by clamped inductive switching measurements of a SiC power module. Moreover, it is applied to determine the maximum permissible gate-source voltage range in compliance with the manufacturer’s voltage rating for a given driver-module combination. In this context a significant extension of the gate drive voltage range and thus an increase of efficiency using impedance specific PWM patterns is demonstrated.



FAU-Autoren / FAU-Herausgeber

März, Martin Prof. Dr.
Lehrstuhl für Leistungselektronik


Autor(en) der externen Einrichtung(en)
Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie (IISB)


Zitierweisen

APA:
März, M., Gerstner, H., Heckel, T., Endruschat, A., Rosskopf, A., & Eckardt, B. (2017). SiC Power Module Loss Reduction by PWM Gate Drive Patterns and Impedance-Optimized Gate Drive Voltages. Albuquerque, NM, US.

MLA:
März, Martin, et al. "SiC Power Module Loss Reduction by PWM Gate Drive Patterns and Impedance-Optimized Gate Drive Voltages." Proceedings of the 2017 WiPDA, Albuquerque, NM 2017.

BibTeX: 

Zuletzt aktualisiert 2018-06-08 um 11:53