Generating and Checking Control Logic in the HDL-Based Design of Reversible Circuits
Wille R, Keszocze O, Othmer L, Thomsen MK, Drechsler R (2017)
Publication Status: Published
Publication Type: Conference contribution, Conference Contribution
Publication year: 2017
Publisher: Institute of Electrical and Electronics Engineers Inc.
Pages Range: 7-12
Article Number: 7977045
Event location: Patna, Indien
ISBN: 9781509025411
DOI: 10.1109/ISED.2016.7977045
Authors with CRIS profile
Involved external institutions
Johannes Kepler Universität (JKU) Linz
Austria (AT)
Deutsches Forschungszentrum für Künstliche Intelligenz (DFKI) GmbH
Germany (DE)
University of Copenhagen
Denmark (DK)
Austria (AT)
Deutsches Forschungszentrum für Künstliche Intelligenz (DFKI) GmbH
Germany (DE)
University of Copenhagen
Denmark (DK)
How to cite
APA:
Wille, R., Keszocze, O., Othmer, L., Thomsen, M.K., & Drechsler, R. (2017). Generating and Checking Control Logic in the HDL-Based Design of Reversible Circuits. In Proceedings of the 6th International Symposium on Embedded Computing and System Design, ISED 2016 (pp. 7-12). Patna, Indien: Institute of Electrical and Electronics Engineers Inc..
MLA:
Wille, Robert, et al. "Generating and Checking Control Logic in the HDL-Based Design of Reversible Circuits." Proceedings of the 6th International Symposium on Embedded Computing and System Design, ISED 2016, Patna, Indien Institute of Electrical and Electronics Engineers Inc., 2017. 7-12.
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