Efficient multicore-aware parallelization strategies for iterative stencil computations

Beitrag in einer Fachzeitschrift


Details zur Publikation

Autorinnen und Autoren: Eitzinger J, Wellein G, Hager G
Zeitschrift: Journal of Computational Science
Verlag: Elsevier BV
Jahr der Veröffentlichung: 2011
Band: 2
Heftnummer: 2
Seitenbereich: 130–137
ISSN: 1877-7503


Abstract


Stencil computations consume a major part of runtime in many scientific simulation codes. As prototypes for this class of algorithms we consider the iterative Jacobi and Gauss-Seidel smoothers and aim at highly efficient parallel implementations for cache-based multicore architectures. Temporal cache blocking is a known advanced optimization technique, which can reduce the pressure on the memory bus significantly. We apply and refine this optimization for a recently presented temporal blocking strategy designed to explicitly utilize multicore characteristics. Especially for the case of Gauss-Seidel smoothers we show that simultaneous multi-threading (SMT) can yield substantial performance improvements for our optimized algorithm on some architectures. © 2011 Elsevier B.V.



FAU-Autorinnen und Autoren / FAU-Herausgeberinnen und Herausgeber

Eitzinger, Jan Dr.
Regionales Rechenzentrum Erlangen (RRZE)
Regionales Rechenzentrum Erlangen (RRZE)
Hager, Georg Dr.
Wellein, Gerhard Prof. Dr.
Professur für Höchstleistungsrechnen


Zitierweisen

APA:
Eitzinger, J., Wellein, G., & Hager, G. (2011). Efficient multicore-aware parallelization strategies for iterative stencil computations. Journal of Computational Science, 2(2), 130–137. https://dx.doi.org/10.1016/j.jocs.2011.01.010

MLA:
Eitzinger, Jan, Gerhard Wellein, and Georg Hager. "Efficient multicore-aware parallelization strategies for iterative stencil computations." Journal of Computational Science 2.2 (2011): 130–137.

BibTeX: 

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