Éricles Rodrigues Sousa


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Project member

(TRR 89: Invasive Computing):
TRR 89: Compilation and Code Generation for Invasive Programs (C03)
Prof. Dr.-Ing. Jürgen Teich
(01/07/2010 - 30/06/2018)

Publications (Download BibTeX)

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Brand, M., Witterauf, M., Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2019). *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing. Concurrency and Computation-Practice & Experience. https://dx.doi.org/10.1002/cpe.5149
Sousa, É., Witterauf, M., Brand, M., Tanase, A.-P., Hannig, F., & Teich, J. (2018). Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. In Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). Milan, Italy.
Sousa, É. (2018). Memory and Interface Architectures for Invasive Tightly Coupled Processor Arrays (Dissertation).
Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2017). A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays. In Proceedings of the International Conference on ReConFigurable Computing and FPGA's (ReConFig). Cancun, Mexico, MX.
Sousa, É., Chakraborty, A., Tanase, A.-P., Hannig, F., & Teich, J. (2017). TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays. Poster presentation at Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, MX.
Henkel, J., Chen, Q., Schmitt-Landsiedel, D., Glocker, E., Sousa, É., Schlichtmann, U.,... Bauer, L. (2016). Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach. it - Information Technology, 58(6), 297-307. https://dx.doi.org/10.1515/itit-2016-0028
Tanase, A.-P., Witterauf, M., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2016). LoopInvader: A Compiler for Tightly Coupled Processor Arrays. In Tool presentation at the University Booth. Dresden, DE.
Gangadharan, D., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2015). Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. In Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR) (pp. 398-403). Pacific Grove, CA, US: IEEE Computer Society.
Sousa, É., Hannig, F., & Teich, J. (2015). Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. In Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, and Achim Rettberg (Eds.), Proceedings of the International Embedded Systems Symposium (IESS) (pp. 1-10). Foz do Iguaçu, BR: Springer International Publishing.
Paul, J., Stechele, W., Oechslein, B., Erhardt, C.P., Schedel, J., Lohmann, D.,... Henkel, J. (2015). Resource-awareness on heterogeneous MPSoCs for image processing. Journal of Systems Architecture, 61(10), 668-680. https://dx.doi.org/10.1016/j.sysarc.2015.09.002

Last updated on 2019-14-06 at 23:51