Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays - Sousa, Éricles; Tanase, Alexandru-Petru; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Paul, Johny; Stechele, Walter; Kröhnert, Manfred; Asfour, Tamim (Proc. 25th Workshop on Parallel Systems and Algorithms, 2013)
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.accele_6

Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays - Sousa, Éricles; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, 2013)
Nowadays, computer vision algorithms have countless application domains. On the one hand, these algorithms are typically computationally demanding, on the other hand, they are often used in embedded systems, which have stringent constraints on, e. g., size or power. In this work, we present the benefits of mapping compute-intensive imaging algorithms on programmable massively parallel processor arrays. More specific, we propose different variants of a combined corner and edge detection algorithm, the Harris Corner Detector (HCD), map these variants onto tightly-coupled processor arrays (TCPAs), and prototype the TCPA architecture, executing the different HCD implementations, in FPGA technology. Because floating-point operations are very costly in FPGAs, we use fixed-point arithmetic in our design, and evaluate our implementation by means of accuracy and performance against two state-of-the-art implementations: (a) the OpenCV library of programming functions for real-time computer vision, using 64-bit floating-point precision, and (b) a 32-bit fixed-point DSP-based embedded system. The accuracy of our work is evaluated by considering the number of corners detected. Here, our approach achieves an average error of less than 1.5% when compared with a reference implementation. Our different variants, trading accuracy for performance, are mapped to the programmable processor elements of a TCPA. Here, the fastest TCPA implementation achieves a 55 times higher frame rate than a state-of-the-art implementation of the HCD on a digital signal processor. Finally, we show how our implementation can be used in the context of a new resource-aware parallel computing paradigm, called invasive computing. Here, an application can adapt itself at run-time in order to satisfy different quality and throughput requirements.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.accura

Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms - Gangadharan, Deepak; Sousa, Éricles; Lari, Vahid; Hannig, Frank; Teich, Jürgen (Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), 2015)
The growing demand of computationally intensive algorithms/applications has resulted in the widespread acceptance of heterogeneous MPSoC platforms. The primary reason for this trend is due to the better performance and power efficiency exhibited by heterogeneous architectures consisting of standard processor cores and hardware accelerators. However, multiple processors accessing shared resources such as cache/memory and buses may lead to significant contention on them, thereby decreasing not only the performance, but also timing predictability. Moreover, the effect of shared resource contention worsens in the presence of multiple application scenarios with different execution and communication bandwidth requirements. To mitigate this problem, we first propose a Dynamic Bus Reconfiguration Policy (DBRP) that decides when to reconfigure a shared bus between Non-Preemptive Fixed Priority (NP-FP) and Time-Division Multiple Access (TDMA) scheduling. The required TDMA slot sizes are computed on-the-fly before NP-FP to TDMA reconfiguration such that deadlines of all Hard Real-Time (HRT) applications are satisfied and all Soft Real-Time (SRT) applications are serviced evenly. Our proposed DBRP has been implemented on a real MPSoC platform consisting of cores connected by the AMBA AHB. The case studies demonstrate that reconfiguration of bus arbitration ensures that communication deadline constraints of HRT applications are maximally satisfied with low hardware and reconfiguration overhead.

A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture - Sousa, Éricles; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Proc. 2013 Conference on Design and Architectures for Signal and Image Processing, 2013)
Continuous software and hardware innovations impose on the one hand a high degree of flexibility from an algorithm and on the other hand it requires that a given processing architecture has the capability to adapt to changing computation patterns at run-time. In this work, we demonstrate how a computer vision application can adapt itself at runtime in order to satisfy different requirements of quality and throughput. For that, we consider an implementation of the Harris Corner Detector on an MPSoC (Multi-Processor System-on-Chip) architecture composed of a quad-core RISC processor and one accelerator based on a programmable massively parallel processor array.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.inform.aproto

A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays - Sousa, Éricles; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (International Conference on ReConFigurable Computing and FPGA's (ReConFig), 2017)

Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach - Henkel, Jörg; Chen, Qingqing; Schmitt-Landsiedel, Doris; Glocker, Elisabeth; Sousa, Éricles; Schlichtmann, Ulf; Herkersdorf, Andreas; Hannig, Frank; Wenzel, Volker; Wagner, Philipp; Sagi, Mark; Wild, Thomas; et al. (it - Information Technology, 2016)

Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study - Sousa, Éricles; Witterauf, Michael; Brand, Marcel; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2018)

LoopInvader: A Compiler for Tightly Coupled Processor Arrays - Tanase, Alexandru-Petru; Witterauf, Michael; Sousa, Éricles; Lari, Vahid; Hannig, Frank; Teich, Jürgen (Tool presentation at the University Booth, 2016)

Memory and Interface Architectures for Invasive Tightly Coupled Processor Arrays - Sousa, Éricles (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2018)

*-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing - Brand, Marcel; Witterauf, Michael; Sousa, Éricles; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Concurrency and Computation-Practice & Experience, 2019)
The fulfillment of non-functional requirements like timing or energy consumption is of utmost importance in many embedded systems and respective applications. Especially, with the introduc- tion of multi-core architectures, the ability to predict non-functional execution qualities becomes more and more difficult, as multiple concurrent application programs may interfere in execution when typcially sharing all the resources. In this paper, we advocate a novel parallel computing paradigm called invasive computing that allows to isolate application programs on multi-core targets. For a presented case study of a cyber-physical real-time control system, we show that invasive computing enables composability that in fact allows to characterize and analyze each ap- plication program statically and independent from each other. More specifically, it is shown that a distributed object detection algorithm for controlling an inverted pendulum and implemented on a heterogeneous invasive multi-processor SoC (MPSoC) is able to provide real-time guarantees as well as reliability requirements on demand. <br
Keywords: Invasive computing; processor arrays; symbolic parallelization; mapping; loop programs

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays - Sousa, Éricles; Hannig, Frank; Teich, Jürgen (Proceedings of the International Embedded Systems Symposium (IESS), 2015)

Resource-Aware Computer Vision Application on Heterogeneous Multi-Tile Architecture. - Sousa, Éricles; Paul, Johny; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Stechele, Walter (Hardware and Software Demo at the University Booth at Design, Automation and Test in Europe (DATE), 2014)

Resource-awareness on heterogeneous MPSoCs for image processing - Paul, Johny; Stechele, Walter; Oechslein, Benjamin; Erhardt, Christoph; Schedel, Jens; Lohmann, Daniel; Schröder-Preikschat, Wolfgang; Kröhnert, Manfred; Asfour, Tamim; Sousa, Éricles; Hannig, Frank; Lari, Vahid; et al. (Journal of Systems Architecture, 2015)
Multiprocessor system-on-chip (MPSoC) designs offer a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. On-chip MPPAs can be used to accelerate low-level image-processing algorithms with massive inherent parallelism. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, among others. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to under-utilization of some type of PEs while overloading others. In this work, we investigate the benefits of using a heterogeneous MPSoC for accelerating various stages within a real-world image-processing algorithm for object-recognition. A case study demonstrates that a resource-aware programming model called Invasive Computing helps to improve the throughput and worst observed latency of the application program, by dynamically mapping applications to different types of PEs available on a heterogeneous MPSo
Keywords: Computer vision; Heterogeneous processor; Image processing; Invasive Computing; MPSoC; Resource awareness

Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays - Sousa, Éricles; Hannig, Frank; Teich, Jürgen; Schlichtmann, Ulf; Chen, Qingqing (In Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES), 2015)
Massively Parallel Processor Arrays (MPPAs) can be nicely used in portable devices such as tablets and smartphones. However, applications running on mobile platforms require a certain performance level or quality (e.g., high-resolution image processing) that need to be satisfied while adhering to a certain power budget and temperature threshold. As a solution to the aforementioned challenges, we consider a resource-aware computing paradigm to exploit runtime adaptation without violating any thermal and/or power constraint in a programmable MPPA. For estimating the power consumption, we developed a mathematical model based on the post-synthesis implementation of an MPPA in different CMOS technologies while the temperature variation was emulated. We showcase our hardware/software mechanism to load new, on-the-fly configurations into the accelerator, considering quality/throughput tradeoffs for image processing applications. The results show that the average power consumption of a Sobel and Laplace operators using different number of processing elements amounts to 1.24mW and 10.35mW, respectively. Furthermore, only 1.64 μs are necessary for configuring a class of MPPA running at 550 MHz.

Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures - Sousa, Éricles; Gangadharan, Deepak; Hannig, Frank; Teich, Jürgen (Proceedings of the EUROMICRO Digital System Design Conference (DSD), 2014)
This paper describes a runtime reconfigurable bus arbitration technique for concurrent applications on heterogeneous MPSoC architectures. Here, a hardware/software approach is introduced as part of a runtime framework that enables selecting and adapting different policies (i. e., fixed-priority, TDMA, and Round-Robin) such that the performance goals of concurrent applications can be satisfied. To evaluate the hardware cost, we compare our proposed solution with respect to a well-known SPARC V8 architecture supporting fixed-priority arbitration. Notably, even providing the flexibility for selecting up to three different policies, our reconfigurable arbiter needs only 25% and 7% more LUTs and slices registers, respectively. The reconfiguration overhead for changing between different policies is 56 cycles and for programming new time slots, only 28 cycles are necessary. For demonstrating the benefits of this reconfiguration framework, we setup a mixed hard/soft real-time scenario by considering four applications with different timeliness requirements. The experimental results show that by reconfiguring the arbiter, less processing elements can be used for achieving a specific target frame rate. Moreover, adjusting the time slots for TDMA, we can speedup a soft real-time algorithm while still satisfying the deadline for hard real-time applications.
Keywords: Concurrent Applications; Heterogeneous MPSoC Architectures; Reconfigurable Bus Arbitration; Runtime

Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor - Paul, Johny; Stechele, Walter; Sousa, Éricles; Lari, Vahid; Hannig, Frank; Teich, Jürgen; Kröhnert, Manfred; Asfour, Tamim (Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP), 2014)
The recent years have shown the emergence of heterogeneous system architecture (HSA), which offers massive computational power assembled into a compact design. Computer vision applications with massive inherent parallelism highly benefits from such heterogeneous processors with on-chip CPU and GPU units. The highly parallel and compute intensive parts of the application program can be mapped to the GPU while the control flow and high level tasks may run on the CPU. However, they pose considerable challenge to software development due to their hybrid architecture. Sharing of resources (GPU or CPU) among applications running concurrently, leads to variations in processing interval and prolonged processing intervals leads to low quality results (frame drops) for computer vision algorithms. In this work, we propose resource-awareness and self organisation within the application layer to adapt to available resources on the heterogeneous processor. The benefits of the new model is demonstrated using a widely used computer vision algorithm called Harris corner detector. A resource-aware runtime-system and a heterogeneous processor were used for evaluation and the results indicate a well constrained processing interval and reduced frame-drops. Our evaluations demonstrate up to 20% improvements in processing rate and accuracy of the detected corner points for Harris corner detectio
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.inform.selfad

TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays - Sousa, Éricles; Chakraborty, Arindam; Tanase, Alexandru-Petru; Hannig, Frank; Teich, Jürgen (Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2017)