Vahid Lari



Organisation


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen


Publications (Download BibTeX)

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Khdr, H., Pagani, S., Rodrigues Sousa, E., Lari, V., Pathania, A., Hannig, F.,... Henkel, J. (2017). Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Transactions on Computers, 66(3), 488--501. https://dx.doi.org/10.1109/TC.2016.2595560
Lari, V. (2016). Invasive Tightly Coupled Processor Arrays. In Springer book series on Computer Architecture and Design Methodologies Singapore: Springer.
Lari, V., Weichslgartner, A., Tanase, A.-P., Witterauf, M., Khosravi, F., Teich, J.,... Becker, J. (2016). Providing Fault Tolerance Through Invasive Computing. it - Information Technology, 58(6), 309-238.
Tanase, A.-P., Witterauf, M., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2016). LoopInvader: A Compiler for Tightly Coupled Processor Arrays. In Tool presentation at the University Booth. Dresden, DE.
Gangadharan, D., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2015). Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. In Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR) (pp. 398-403). Pacific Grove, CA, US: IEEE Computer Society.
Lari, V. (2015). Invasive Tightly Coupled Processor Arrays (Dissertation).
Lari, V., Tanase, A.-P., Teich, J., Witterauf, M., Khosravi, F., Hannig, F., & Meyer, B. (2015). A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (pp. 1-8). Montreal, CA: Institute of Electrical and Electronics Engineers Inc..
Paul, J., Stechele, W., Oechslein, B., Erhardt, C., Schedel, J., Lohmann, D.,... Henkel, J. (2015). Resource-awareness on heterogeneous MPSoCs for image processing. Journal of Systems Architecture, 61(10), 668-680. https://dx.doi.org/10.1016/j.sysarc.2015.09.002
Tanase, A.-P., Witterauf, M., Teich, J., Hannig, F., & Lari, V. (2015). On-demand fault-tolerant loop processing on massively parallel processor arrays. In In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 194-201). Toronto, CA: Institute of Electrical and Electronics Engineers Inc..
Teich, J., Boppu, S., Hannig, F., & Lari, V. (2015). Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays. In Luk, Wayne, Constantinides, George A. (Eds.), Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung (pp. 167-206).

Last updated on 2017-02-01 at 01:01