Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Martensstraße 3
91058 Erlangen

Related Project(s)

DIME: DIME - Datenlokale Iterationsverfahren zur effizienten Lösung partieller Differentialgleichungen
Arndt Bode; Prof. Dr. Ulrich Rüde
(01/06/2000 - 30/04/2006)

Publications (Download BibTeX)

Go to first page Go to previous page 1 of 7 Go to next page Go to last page

Talati, N., Ben-Hur, R., Wald, N., Haj-Ali, A., Prabahar, J.R., & Kvatinsky, S. (2020). mMPU—A Real Processing-in-Memory Architecture to Combat the von Neumann Bottleneck. In Manan suri (Eds.), Applications of Emerging Memory Technology. (pp. 191-213). Springer Singapore.
Heller, T., Lelbach, B.A., Huck, K.A., Biddiscombe, J., Grubel, P., Koniges, A.E.,... Kaiser, H. (2019). Harnessing billions of tasks for a scalable portable hydrodynamic simulation of the merger of two stars. International Journal of High Performance Computing Applications, 33(4), 699-715. https://dx.doi.org/10.1177/1094342018819744
Rachuj, S., Reichenbach, M., & Fey, D. (2019). A generic functional simulation of heterogeneous systems. In Martin Schoeberl, Thilo Pionteck, Sascha Uhrig, Jürgen Brehm, Christian Hochberger (Eds.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (pp. 128-141). Copenhagen, DK: Springer Verlag.
Biglari, M., Lieske, T., & Fey, D. (2019). Reducing Hibernation Energy and Degradation in Bipolar ReRAM-Based Non-Volatile Processors. IEEE Transactions on Nanotechnology. https://dx.doi.org/10.1109/TNANO.2019.2922363
Häublein, K., Brückner, W., Vaas, S., Rachuj, S., Reichenbach, M., & Fey, D. (2019). Utilizing PYNQ for Accelerating Image Processing Functions in ADAS Applications. In Trinitis, Carsten ; Pionteck, Thilo (Eds.), Proceedings of the ARCS 2019: 32nd International Conference on Architecture of Computing Systems (pp. 93-100). Copenhagen, DK: VDE Verlag.
Aguilar, X., Jordan, H., Heller, T., Hirsch, A., Fahringer, T., & Laure, E. (2019). An On-Line Performance Introspection Framework for Task-Based Runtime Systems. In João M.F. Rodrigues, Pedro J.S. Cardoso, Jânio Monteiro, Roberto Lam, Jack J. Dongarra, Valeria V. Krzhizhanovskaya, Michael H. Lees, Peter M.A. Sloot (Eds.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (pp. 238-252). Faro, PT: Springer Verlag.
Bauer, W., Holzinger, P., Reichenbach, M., Vaas, S., Hartke, P., & Fey, D. (2019). Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems. In Mencagli G, B. Heras D, Cardellini V, Casalicchio E, Jeannot E, Wolf F, Salis A, Schifanella C, Manumachu RR, Ricci L, Beccuti M, Antonelli L, Garcia Sanchez JD, Scott SL (Eds.), Euro-Par 2018: Parallel Processing Workshops (pp. 733-744). Cham: Springer International Publishing.
Reuben, J.R., Fey, D., & Wenger, C. (2019). A modeling methodology for resistive RAM based on stanford-PKU model with extended multilevel capability. IEEE Transactions on Nanotechnology, 18, 647-656. https://dx.doi.org/10.1109/TNANO.2019.2922838
Bauer, W., Holzinger, P., Rachuj, S., Häublein, K., Reichenbach, M., & Fey, D. (2019). Evaluating HSA-Compatible Heterogeneous Systems for ADAS Applications. In Trinitis, Carsten; Pionteck, Thilo (Eds.), Workshop Proceedings (pp. 129-136). Copenhagen, Denmark.
Knödtel, J., Schwabe, W., Lieske, T., Reichenbach, M., & Fey, D. (2018). A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs. In 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) (pp. 46-53-53). Platja D’Aro, ES.
Rachuj, S., Reichenbach, M., Vaas, S., & Fey, D. (2018). Autonomous Driving in the Curriculum of Computer Architecture. In Proceedings of the 12th European Workshop on Microelectronics Education. Braunschweig, DE.
Schwarzmeier, C., Ditter, A., & Fey, D. (2018, September). Distributed Asynchronous Jacobi Methods. Poster presentation at CoSaS 2018 International Symposium on Computational Science at Scale, Erlangen.
Holzinger, P., Reichenbach, M., & Fey, D. (2018). A New Generic HLS Approach for Heterogeneous Computing: On the Feasibility of High-Level Synthesis in HSA-Compatible Systems. In Mudge Trevor, Pnevmatikatos Dionisios N. (Eds.), SAMOS XVIII: 2018 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (pp. 18-27). Pythagorion, Samos Island, GR: New York, NY, USA: ACM.
Rachuj, S., Herglotz, C., Reichenbach, M., Kaup, A., & Fey, D. (2018). A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model. In Mladen Berekovic, Rainer Buchty, Heiko Hamann, Dirk Koch, Thilo Pionteck (Eds.), 31st International Conference on Architecture of Computing Systems, ARCS 2018 (pp. 85-96). Braunschweig: Springer.
Fey, D., & Hannig, F. (2018). Special Issue on Heterogeneous Real-Time Image Processing. Journal of Real-Time Image Processing, 14(3), 513-515. https://dx.doi.org/10.1007/s11554-018-0763-2
Wust, D., Fey, D., & Knödtel, J. (2018). A programmable ternary CPU using hybrid CMOS/memristor circuits. International Journal of Parallel, Emergent and Distributed Systems, 1--21. https://dx.doi.org/10.1080/17445760.2017.1422251
Lieske, T., Uhring, W., Dumas, N., Skilitsi, A.I., Leonard, J., & Fey, D. (2018). Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications. Journal of Signal Processing Systems. https://dx.doi.org/10.1007/s11265-018-1372-9
Widerspick, C., Bauer, W., & Fey, D. (2018). Latency Measurements for an Emulation Platform on Autonomous Driving Platform NVIDIA Drive PX2. In ARCS Workshop 2018; 31th International Conference on Architecture of Computing Systems (pp. 1-8-8). Braunschweig, Germany,: VDE.
Biglari, M., Lieske, T., & Fey, D. (2018). High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. In Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures (pp. 19 - 24). Athens, Greece: New York, NY, USA: ACM.
Lieske, T., Biglari, M., & Fey, D. (2018). Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs. In Proceedings of the International Symposium on Memory Systems (pp. 259-268). Alexandria, Virginia, US: New York, NY, USA: ACM.

Last updated on 2019-24-04 at 10:22