Lehrstuhl für Informatik 3 (Rechnerarchitektur)

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Publications (Download BibTeX)

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Knödtel, J., Schwabe, W., Lieske, T., Reichenbach, M., & Fey, D. (2018). A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs. In 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) (pp. 46-53-53). Platja D’Aro, ES.
Rachuj, S., Herglotz, C., Reichenbach, M., Kaup, A., & Fey, D. (2018). A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model. In Mladen Berekovic, Rainer Buchty, Heiko Hamann, Dirk Koch, Thilo Pionteck (Eds.), 31st International Conference on Architecture of Computing Systems, ARCS 2018 (pp. 85-96). Braunschweig: Springer.
Fey, D., & Hannig, F. (2018). Special Issue on Heterogeneous Real-Time Image Processing. Journal of Real-Time Image Processing, 14(3), 513-515. https://dx.doi.org/10.1007/s11554-018-0763-2
Wust, D., Fey, D., & Knödtel, J. (2018). A programmable ternary CPU using hybrid CMOS/memristor circuits. International Journal of Parallel, Emergent and Distributed Systems, 1--21. https://dx.doi.org/10.1080/17445760.2017.1422251
Lieske, T., Uhring, W., Dumas, N., Skilitsi, A.I., Leonard, J., & Fey, D. (2018). Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications. Journal of Signal Processing Systems. https://dx.doi.org/https://doi.org/10.1007/s11265-018-1372-9
Vaas, S., Ulbrich, P., Reichenbach, M., & Fey, D. (2018). Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands. Journal of Signal Processing Systems.
Reichenbach, M., Holzinger, P., Häublein, K., Lieske, T., Blinzer, P., & Fey, D. (2018). Heterogeneous Computing Utilizing FPGAs. Journal of Signal Processing Systems. https://dx.doi.org/10.1007/s11265-018-1382-7
Herglotz, C., Springer, D., Reichenbach, M., Stabernack, B., & Kaup, A. (2018). Modeling the Energy Consumption of the HEVC Decoding Process. IEEE Transactions on Circuits and Systems For Video Technology, 28, 217-229. https://dx.doi.org/10.1109/TCSVT.2016.2598705
Widerspick, C., Bauer, W., & Fey, D. (2018). Latency Measurements for an Emulation Platform on Autonomous Driving Platform NVIDIA Drive PX2. In ARCS Workshop 2018; 31th International Conference on Architecture of Computing Systems (pp. 1-8-8). Braunschweig, Germany,: VDE.
Biglari, M., Lieske, T., & Fey, D. (2018). High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States.
Söll, C., Reichenbach, M., Röber, J., Hagelauer, A., Weigel, R., & Fey, D. (2018). Case Study on Memristor-Based Multilevel Memories. International Journal of Circuit Theory and Applications, 46(1), 99-112. https://dx.doi.org/10.1002/cta.2379
Lieske, T., Biglari, M., & Fey, D. (2018). Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs. In Proceedings of the International Symposium on Memory Systems. Alexandria, Virginia, US.
Rachuj, S., Bauer, W., & Fey, D. (2018). Evaluation of a Sensor Fusion Algorithm on a Real-Time Processor. In AmE 2018 - Automotive meets Electronics (pp. 44-48). Dortmund.
Streit, F.-J., Letras, M., Schid, M., Falk, J., Wildermann, S., & Teich, J. (2017). High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems. Stanford, US: Association for Computing Machinery.
Kuckuk, S., Leitenmaier, L., Schmitt, C., Schönwetter, D., Köstler, H., & Fey, D. (2017). Towards Virtual Hardware Prototyping for Generated Geometric Multigrid Solvers.
Vaas, S., Ulbrich, P., Reichenbach, M., & Fey, D. (2017). The Best of Both: High-performance and Deterministic Real-Time Executive by Application-Specific Multi-Core SoCs. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP '17) (pp. 1-6). Dresden, DE: Los Alamitos, CA: IEEE Computer Society Press.
Hofmann, J., Fey, D., Riedmann, M., Eitzinger, J., Hager, G., & Wellein, G. (2017). Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors. Concurrency and Computation-Practice & Experience, 29(9). https://dx.doi.org/10.1002/cpe.3921
Biglari, M., & Fey, D. (2017, March). A Non-Volatile Flip-Flop Using Memristive Voltage Divider. Poster presentation at IEEE/ACM Design Automation and Test in Europe (DATE), Workshop on Emerging Memory Solutions - Technology, Manufacturing, Architectures, Design and Test, Lausanne, CH.
Hofmann, J., Hager, G., Wellein, G., & Fey, D. (2017). An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors. In High Performance Computing. ISC 2017. Lecture Notes in Computer Science, vol 10266. Frankfurt: Cham: Springer.
Lieske, T., Pfundt, B., Vaas, S., Reichenbach, M., & Fey, D. (2017). System on Chip Generation for Multi-Sensor and Sensor Fusion Applications. In Proceedings of the 17th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (pp. 20-29). Island of Samos, Greece.

Last updated on 2017-28-06 at 15:18