Lehrstuhl für Informatik 3 (Rechnerarchitektur)

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Publications (Download BibTeX)

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Fey, D., & Hannig, F. (2018). Special Issue on Heterogeneous Real-Time Image Processing. Journal of Real-Time Image Processing, 14(3), 513-515. https://dx.doi.org/10.1007/s11554-018-0763-2
Wust, D., Fey, D., & Knödtel, J. (2018). A programmable ternary CPU using hybrid CMOS/memristor circuits. International Journal of Parallel, Emergent and Distributed Systems, 1--21. https://dx.doi.org/10.1080/17445760.2017.1422251
Herglotz, C., Springer, D., Reichenbach, M., Stabernack, B., & Kaup, A. (2018). Modeling the Energy Consumption of the HEVC Decoding Process. IEEE Transactions on Circuits and Systems For Video Technology, 28, 217-229. https://dx.doi.org/10.1109/TCSVT.2016.2598705
Söll, C., Reichenbach, M., Röber, J., Hagelauer, A., Weigel, R., & Fey, D. (2018). Case Study on Memristor-Based Multilevel Memories. International Journal of Circuit Theory and Applications, 46(1), 99-112. https://dx.doi.org/10.1002/cta.2379
Rachuj, S., Bauer, W., & Fey, D. (2018). Evaluation of a Sensor Fusion Algorithm on a Real-Time Processor. In AmE 2018 - Automotive meets Electronics (pp. 44-48). Dortmund.
Vaas, S., Ulbrich, P., Reichenbach, M., & Fey, D. (2018). Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands. Journal of Signal Processing Systems.
Streit, F.-J., Letras, M., Schid, M., Falk, J., Wildermann, S., & Teich, J. (2017). High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems. Stanford, US: Association for Computing Machinery.
Biglari, M., & Fey, D. (2017). Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flops. In MEMSYS '17 Proceedings of the International Symposium on Memory Systems (pp. 217-222). Washington DC, USA, US: New York, NY, USA: ACM.
Kuckuk, S., Leitenmaier, L., Schmitt, C., Schönwetter, D., Köstler, H., & Fey, D. (2017). Towards Virtual Hardware Prototyping for Generated Geometric Multigrid Solvers.
Vaas, S., Ulbrich, P., Reichenbach, M., & Fey, D. (2017). The Best of Both: High-performance and Deterministic Real-Time Executive by Application-Specific Multi-Core SoCs. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP '17) (pp. 1-6). Dresden, DE: Los Alamitos, CA: IEEE Computer Society Press.
Biglari, M., & Fey, D. (2017, March). A Non-Volatile Flip-Flop Using Memristive Voltage Divider. Poster presentation at IEEE/ACM Design Automation and Test in Europe (DATE), Workshop on Emerging Memory Solutions - Technology, Manufacturing, Architectures, Design and Test, Lausanne, Switzerland, CH.
Wust, D., Söll, C., & Fey, D. (2017). A fast general purpose CPU utilizing signed-digit encoding and multi-bit memristors.
Wust, D., Biglari, M., Knödtel, J., Reichenbach, M., Söll, C., & Fey, D. (2017). Prototyping memristors in digital system with an FPGA-based testing environment. In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on. Thessaloniki, Greece, GR: IEEE.
Hofmann, J., Hager, G., Wellein, G., & Fey, D. (2017). An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors. In High Performance Computing. ISC 2017. Lecture Notes in Computer Science, vol 10266. Frankfurt: Cham: Springer.
Rachuj, S., Hartmann, C., & Fey, D. (2017). Evaluation of a Processor Simulator Exemplified by a Radar Processing Algorithm. In Workshop Proceedings (pp. 96-100). Wien: Wien: VDE Verlag.
Lieske, T., Schuklin, D., Hohnloser, D., Reichenbach, M., Pfundt, B., Fey, D., & Weigel, R. (2016). Smart Sensor Framework: A Pressure Sensor for Smart Home Applications. Nürnberg, DE.
Fey, D., Reichenbach, M., Söll, C., Biglari, M., Röber, J., & Weigel, R. (2016). Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits. Washington, USA: Association for Computing Machinery.
Söll, C., Shi, L., Röber, J., Reichenbach, M., Weigel, R., & Hagelauer, A. (2016). Low-Power Analog Smart Camera Sensor for Edge Detection. Phoenix, USA.
Richter, F., Fey, D., & Hain, S. (2016). FPGA-aware Transformations of LLVM-IR. In The First International Conference on Advances in Signal, Image and Video Processing (pp. 15-20). Lisbon, PT.
Steg, A., Reichenbach, M., Söll, C., Shi, L., Maier, A., & Rieß, C. (2016). Dynamic Pixel Binning allows Spatial and Angular Resolution Tradeoffs to improve Image Quality in X-Ray C-Arm CT. (pp. 577-580). Prague.

Last updated on 2017-28-06 at 15:18