Architecture and Compiler Design

Environment Mapping Using Massively Parallel Architectures (2017) Fickenscher J, Bouzouraa ME, Hannig F, Teich J Conference contribution, Abstract of a poster Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays (2017) Tanase AP, Witterauf M, Teich J, Hannig F Journal article, Original article Generating FPGA-based Image Processing Accelerators with Hipacc (2017) Reiche O, Özkan MA, Membarth R, Teich J, Hannig F Conference contribution, Conference Contribution A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis (2017) Özkan MA, Reiche O, Hannig F, Teich J Conference contribution Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing (2017) Özkan MA, Reiche O, Hannig F, Teich J Conference contribution Efficiency in ILP Processing by Using Orthogonality (2017) Brand M, Hannig F, Tanase AP, Teich J Conference contribution, Abstract of a poster Auto-vectorization for Image Processing DSLs (2017) Reiche O, Kobylko C, Hannig F, Teich J Conference contribution, Conference Contribution Trends in Data Locality Abstractions for HPC Systems (2017) Unat D, Dubey A, Hoefler T, Shalf J, Abraham M, Bianco M, Chamberlain BL, et al. Journal article, Short survey Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors (2017) Brand M, Hannig F, Tanase AP, Teich J Conference contribution, Original article High Performance Network-on-Chip Simulation by Interval-based Timing Predictions (2017) Roloff S, Hannig F, Teich J Conference contribution, Conference Contribution