Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs

Sabih M, Karim A, Wittmann J, Hannig F, Teich J (2025)

Publication Language: English

Publication Type: Other publication type

Publication year: 2025

Edited Volumes: The Computing Research Repository (CoRR)

DOI: 10.48550/arXiv.2504.19659

Authors with CRIS profile

Muhammad Sabih Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Abrarul Karim Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jakob Wittmann Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Frank Hannig Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

How to cite

APA:

Sabih, M., Karim, A., Wittmann, J., Hannig, F., & Teich, J. (2025). Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs.

MLA:

Sabih, Muhammad, et al. Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. 2025.

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