Wu Y, Mammadzada F, Westring K, Neves Rodrigues J (2026)
Publication Type: Conference contribution
Publication year: 2026
Publisher: Institute of Electrical and Electronics Engineers Inc.
Conference Proceedings Title: 24th IEEE Interregional NEWCAS Conference, NEWCAS 2026 - Proceedings
Event location: Chicoutimi, QC, CAN
ISBN: 9798331544133
DOI: 10.1109/NewCAS64543.2026.11674051
The Posit number system features tapered precision, providing higher accuracy for values near unity while maintaining a wide dynamic range, making the format an attractive alternative to IEEE 754 for machine-learning workloads. This work presents CPAU, a unified and configurable Posit arithmetic architecture that integrates a quire-based MAC unit and a general-purpose execution unit supporting addition, multiplication, division, exponential, and square root. CPAU employs a shared decode-execute-encode pipeline across all operators, substantially reducing hardware cost while preserving accuracy in serial computations. A dedicated exponential unit enables full softmax evaluation directly in the Posit domain without format conversions. Synthesis in a 22 nm technology demonstrates significant area improvements of more than 34% and 50% for multiplier and adder area, respectively. Moreover, the implementation of exponential function provides the functionality required for inference and training.
APA:
Wu, Y., Mammadzada, F., Westring, K., & Neves Rodrigues, J. (2026). CPAU: A Hardware Efficient Configurable Posit Arithmetic Unit. In 24th IEEE Interregional NEWCAS Conference, NEWCAS 2026 - Proceedings. Chicoutimi, QC, CAN: Institute of Electrical and Electronics Engineers Inc..
MLA:
Wu, Yue, et al. "CPAU: A Hardware Efficient Configurable Posit Arithmetic Unit." Proceedings of the 24th IEEE Interregional NEWCAS Conference, NEWCAS 2026, Chicoutimi, QC, CAN Institute of Electrical and Electronics Engineers Inc., 2026.
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