Silicon-Based Evaluation of CSD Arithmetic in a RISC-V Processor Using Open-Source ASIC Flow

Ebrahimiazandaryani F, Kupfer M, Fey D (2026)

Publication Type: Conference contribution

Publication year: 2026

Journal

Proceedings - IEEE International Symposium on Circuits and Systems Institute of Electrical and Electronics Engineers

Publisher: Institute of Electrical and Electronics Engineers Inc.

Pages Range: 1699-1703

Conference Proceedings Title: Proceedings - IEEE International Symposium on Circuits and Systems

Event location: Shanghai

ISBN: 9798331577698

DOI: 10.1109/ISCAS66217.2026.11561916

Abstract

This paper presents the ASIC implementation of NOVACore, a high-performance embedded RISC-V processor that integrates Canonical Signed Digit (CSD) arithmetic to enable carry-free addition and subtraction within its execution pipeline. This architectural enhancement significantly improves computational efficiency in arithmetic-intensive embedded workloads. To the best of our knowledge, this work provides the first silicon-based evaluation of CSD arithmetic in a RISC-V core, implemented using a fully open-source ASIC flow targeting the IHP 130 nm technology. Experimental results show that NOVACore, leveraging its CSD-based pipelined execution unit, achieves up to 31% higher throughput than the widely used VexRiscv at the same frequency. This performance comes with 43% area and 82% power overheads, primarily due to the redundant nature of the CSD representation, which increases routing complexity and placement density in NOVACore's execution stage. These results validate the practical viability of CSD arithmetic for improving arithmetic performance in RISC-V processors while contributing to the broader goal of supporting open and accessible ASIC design using open-source toolchains.

Authors with CRIS profile

Farhad Ebrahimiazandaryani Lehrstuhl für Informatik 3 (Rechnerarchitektur) Michael Kupfer Lehrstuhl für Informatik 3 (Rechnerarchitektur) Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

How to cite

APA:

Ebrahimiazandaryani, F., Kupfer, M., & Fey, D. (2026). Silicon-Based Evaluation of CSD Arithmetic in a RISC-V Processor Using Open-Source ASIC Flow. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1699-1703). Shanghai, CN: Institute of Electrical and Electronics Engineers Inc..

MLA:

Ebrahimiazandaryani, Farhad, Michael Kupfer, and Dietmar Fey. "Silicon-Based Evaluation of CSD Arithmetic in a RISC-V Processor Using Open-Source ASIC Flow." Proceedings of the 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026, Shanghai Institute of Electrical and Electronics Engineers Inc., 2026. 1699-1703.

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