FeMFET-based High-Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks

Karim A, Darne B, Matrangolo PA, Falk J, O'Connor I, Marchand C, Bosio A, Teich J (2026)

Publication Type: Journal article

Publication year: 2026

Journal

Microprocessors and Microsystems Elsevier

Abstract

In this paper, we consider efficient hardware implementations of dataflow networks in the context of intermittent computing. While some system-level design methodologies exist to synthesize a given network directly into a hardware implementation for maximum processing speed, they do not address additional challenges posed by intermittent computing, such as ensuring reliable operation and meeting tight power constraints. Indeed, a key limitation of existing approaches is the significant latency overhead incurred when backing up internal states, thus severely impacting achievable processing speeds. To address these challenges, a novel memory cell design is presented that supports both volatile and non-volatile operating modes at a fine-grained level, enabling a local and concurrent retention of internal states. The proposed memory cell is based on ferroelectric FeMFET technology. First, we describe the circuit and protocol for backing up volatile data to non-volatile storage upon reception of a shutdown signal and restoring the state when a wakeup signal is asserted. This hybrid cell is subsequently characterized, and its reliability with respect to process variations and fluctuations in operating conditions evaluated. Finally, this hybrid memory cell is integrated into the design of dataflow actors for state retention during intermittent computing and compared against a scan-chain-based retention technique in terms of power and latency savings, achieving up to 88 % power savings.

Authors with CRIS profile

Abrarul Karim Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Joachim Falk Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design) Jürgen Teich Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Related research project(s)

Automatic Cross-Layer Synthesis of High Performance, (Ultra-)Low Power Hardware Implementations from Data Flow Specifications by Integration of Emerging FeFET Technology (HiLoDa Nets) March 1, 2024 - March 1, 2027

Involved external institutions

Université Claude Bernard Lyon 1 (UCB) FR France (FR)

How to cite

APA:

Karim, A., Darne, B., Matrangolo, P.-A., Falk, J., O'Connor, I., Marchand, C.,... Teich, J. (2026). FeMFET-based High-Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks. Microprocessors and Microsystems.

MLA:

Karim, Abrarul, et al. "FeMFET-based High-Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks." Microprocessors and Microsystems (2026).

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