Multiplier-Free In-Memory Vector-Matrix Multiplication Using Distributed Arithmetic

Zeller F, Reuben JR, Fey D (2025)

Publication Type: Conference contribution

Publication year: 2025

Publisher: Institute of Electrical and Electronics Engineers Inc.

Pages Range: 718-726

Conference Proceedings Title: Proceedings - 2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2025

Event location: Singapore SG

ISBN: 9798331565718

DOI: 10.1109/MCSoC67473.2025.00116

Abstract

Vector-Matrix Multiplication (VMM) is the fundamental and frequently required computation in inference of Neural Networks (NN). Due to the large data movement required during inference, VMM can benefit greatly from in-memory computing. However, ADC/DACs required for in-memory VMM consume significant power and area. 'Distributed Arithmetic (DA)', a technique in computer architecture prevalent in 1980s was used to achieve inner product or dot product of two vectors without using a hard-wired multiplier when one of the vectors is a constant. In this work, we extend the DA technique to multiply an input vector with a constant matrix. By storing the sum of the weights in memory, DA achieves VMM using shift-and-add circuits in the periphery of ReRAM memory. We verify functional and also estimate non-functional properties (latency, energy, area) by performing transistor-level simulations. Using energy-efficient sensing and fine grained pipelining, our approach achieves 4.5 × less latency and 12 × less energy than VMM performed in memory conventionally by bit slicing. Furthermore, DA completely eliminated the need for power-hungry ADCs which are the main source of area and energy consumption in the current VMM implementations in memory.

Authors with CRIS profile

Felix Zeller Lehrstuhl für System-on-Chip John Reuben Prabahar Lehrstuhl für Informatik 3 (Rechnerarchitektur) Dietmar Fey Lehrstuhl für Informatik 3 (Rechnerarchitektur)

How to cite

APA:

Zeller, F., Reuben, J.R., & Fey, D. (2025). Multiplier-Free In-Memory Vector-Matrix Multiplication Using Distributed Arithmetic. In Proceedings - 2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2025 (pp. 718-726). Singapore, SG: Institute of Electrical and Electronics Engineers Inc..

MLA:

Zeller, Felix, John Reuben Reuben, and Dietmar Fey. "Multiplier-Free In-Memory Vector-Matrix Multiplication Using Distributed Arithmetic." Proceedings of the 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2025, Singapore Institute of Electrical and Electronics Engineers Inc., 2025. 718-726.

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