Scheller K, Vilyuk K, Hetterle P, Weninger J, Engelmann A, Weigel R, Schrotz AM, Franchi N (2026)
Publication Type: Conference contribution, Conference Contribution
Publication year: 2026
Publisher: IEEE
ISBN: 979-8-3315-3455-4
URI: https://ieeexplore.ieee.org/document/11378979
DOI: 10.1109/APMC65046.2025.11378979
This paper presents a non-primitive pseudo-random binary sequence (PRBS) generator for sensing application, implemented using ten true single-phase clock (TSPC) flip-flops (FF) configured as a linear feedback shift register (LFSR). The feedback is applied after the tenth and ninth FF using an exclusive OR (XOR) operation, resulting in a shortened sequence length of 889. The PRBS circuit is implemented in a 12 nm FinFET bulk technology, occupying a core area of 22 µm2. It operates at a maximum data rate of 20 GBit/s with a supply voltage of 0.8 V. The total power consumption of the breakout circuit, including support circuitry is 3.52 mW. Whilst the the LFSR core power consumption is 0.72 mW. The PRBS achieves a figure of merit (FoM) of 3.67 fJ/bit based on the maximum data rate and power consumption.
APA:
Scheller, K., Vilyuk, K., Hetterle, P., Weninger, J., Engelmann, A., Weigel, R.,... Franchi, N. (2026). A Low-Power TSPC-PRBS Generator in 12 nm FinFET Bulk CMOS. In Proceedings of the 2025 IEEE Asia-Pacific Microwave Conference. Jeju, KR: IEEE.
MLA:
Scheller, Kai, et al. "A Low-Power TSPC-PRBS Generator in 12 nm FinFET Bulk CMOS." Proceedings of the 2025 IEEE Asia-Pacific Microwave Conference, Jeju IEEE, 2026.
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