An 18× Time-Interleaved 12-bit 6-GS/s SAR ADC System With On-Chip Mismatch Correction in 28-nm CMOS Technology

Linnhoff S, Buballa F, Sippel E, Reinhold M, Vossiek M, Gerfers F (2026)

Publication Type: Journal article

Publication year: 2026

Journal

IEEE Transactions on Microwave Theory and Techniques Institute of Electrical and Electronics Engineers (IEEE)

Book Volume: 74

Pages Range: 199-210

Journal Issue: 1

DOI: 10.1109/TMTT.2025.3622376

Abstract

This article presents a wideband 12-bit 6-GS/s time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a standard 28-nm technology addressing radar, wireless, and instrumentation applications. The ADC system makes use of a wideband front-end (FE) featuring two subsequent ranks of pseudo-differential push–pull input buffers to distribute the input signal to a total of 19 12-bit 375-MS/s SAR-ADC lanes (18 TI lanes plus one additional reference ADC utilized for calibration purposes only). This topology enables large track-and-hold (T/H) bandwidth and linearity while simultaneously mitigating input and inter-lane kickback effects. Each SAR-ADC lane takes advantage of several conversion speed and linearity enhancing techniques, such as a sub-2 radix split-capacitive digital-to-analog converter (CDAC) with about 10% overrange, a distributed sample switch implemented as an isolating T-switch and a fully loop-unrolled comparator architecture. This way, the lane conversion rate and accuracy is improved, while suppressing comparator offset-mismatch effects thanks to the chosen architecture. Furthermore, the ADC system features an on-chip digital calibration engine to correct CDAC mismatches as well as inter-channel mismatch effects such as gain, offset, and sample-phase mismatch. Measurement results reveal an SNDR and SFDR of 50 dB and 62.8 dBc, respectively, for a 1 Vppd input signal across the entire 3-GHz Nyquist-band. The ADC core combined with the input buffers, the on-chip reference voltage generator, clock distribution, digital calibration engine, and JESD204B SerDes draws a total of 2.5 W from four power supplies (1, 1.8, 2.5, and −1.3 V), resulting in a Schreier figure-of-merit (FoMs) of 143/141 dB for low- and high-frequency sine wave inputs.

Authors with CRIS profile

Erik Sippel Lehrstuhl für Hochfrequenztechnik (LHFT) Martin Vossiek Lehrstuhl für Hochfrequenztechnik (LHFT)

Involved external institutions

Technische Universität Berlin DE Germany (DE) Robert Bosch GmbH DE Germany (DE)

How to cite

APA:

Linnhoff, S., Buballa, F., Sippel, E., Reinhold, M., Vossiek, M., & Gerfers, F. (2026). An 18× Time-Interleaved 12-bit 6-GS/s SAR ADC System With On-Chip Mismatch Correction in 28-nm CMOS Technology. IEEE Transactions on Microwave Theory and Techniques, 74(1), 199-210. https://doi.org/10.1109/TMTT.2025.3622376

MLA:

Linnhoff, Sebastian, et al. "An 18× Time-Interleaved 12-bit 6-GS/s SAR ADC System With On-Chip Mismatch Correction in 28-nm CMOS Technology." IEEE Transactions on Microwave Theory and Techniques 74.1 (2026): 199-210.

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