Schlögl T, Fey D (2026)
Publication Type: Conference contribution
Publication year: 2026
Publisher: Springer Science and Business Media Deutschland GmbH
Book Volume: 15839 LNCS
Pages Range: 34-47
Conference Proceedings Title: Lecture Notes in Computer Science
Event location: Kiel, DEU
ISBN: 9783032032805
DOI: 10.1007/978-3-032-03281-2_3
Addition using a ternary signed digit (SD) number representation, i.e. using digits –1, 0 and 1, has the advantage of being computable in O(1) compared to O(n) in standard binary addition using ripple carry adders (RCAs). Therefore, in the past proposals were made how to implement SD adders in Field Programmable Gate Arrays (FPGAs). However, this work is some years old and used older FPGAs with only 4-bit input modules. We propose two different implementations of binary coded ternary SD number additions on Ultrascale FPGAs from Xilinx/AMD and compare them to standard binary addition concerning resource usage and delay. Furthermore, our solutions use newest FPGA technology and improve on previous solutions in literature which are based on less efficient FPGA technology. The first approach is purely based on lookup tables (LUTs). The second one tries to reduce LUT usage by exploiting so called carry chains, which are extremely fast and normally only used to implement binary RCAs. We show that using ternary SD addition increases the resource usage compared to binary RCAs but allows higher addition clock frequencies independent of the number of digits. The implementation incorporating carry chains reduces the number of LUTs compared to our naive LUT based approach and other previously proposed approaches by 50% while maintaining a comparable delay that is better than for standard binary addition.
APA:
Schlögl, T., & Fey, D. (2026). Ternary Signed Digit Addition on Field Programmable Gate Arrays. In Sven Tomforde, Christian Krupitzer, Stéphane Vialle, Estela Suarez, Thilo Pionteck (Eds.), Lecture Notes in Computer Science (pp. 34-47). Kiel, DEU: Springer Science and Business Media Deutschland GmbH.
MLA:
Schlögl, Thomas, and Dietmar Fey. "Ternary Signed Digit Addition on Field Programmable Gate Arrays." Proceedings of the 38th International Conference on Architecture of Computing Systems, ARCS 2025, Kiel, DEU Ed. Sven Tomforde, Christian Krupitzer, Stéphane Vialle, Estela Suarez, Thilo Pionteck, Springer Science and Business Media Deutschland GmbH, 2026. 34-47.
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