Andrich C, Bauer J, Grose P, Ihlow A, Galdo GD (2018)
Publication Type: Conference contribution
Publication year: 2018
Publisher: IEEE Computer Society
Book Volume: 2018-September
Conference Proceedings Title: IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication, ISPCS
Event location: Geneva, CHE
ISBN: 9781538642627
DOI: 10.1109/ISPCS.2018.8543066
We propose a concept for accurate network time synchronization. In comparison to NTPv4 and PTPd, which use a closed-loop design with a single loop filter, our approach splits the task into two fundamental aspects: First, matching the local clock's frequency to the reference frequency is enforced (syntonization). Second, the remaining constant offset between both clocks is minimized (synchronization). We suggest syntonization with a frequency locked loop (FLL) using an open-loop design and synchronization with an additional feedback phase locked loop (PLL). This concept of a time locked loop is advantageous, as it allows faster clock synchronization (smaller settling times) compared to a joint closed-loop design, while furthermore avoiding transient oscillations.
APA:
Andrich, C., Bauer, J., Grose, P., Ihlow, A., & Galdo, G.D. (2018). A Fast and Stable Time Locked Loop for Network Time Synchronization with Parallel FLL and PLL. In IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication, ISPCS. Geneva, CHE: IEEE Computer Society.
MLA:
Andrich, Carsten, et al. "A Fast and Stable Time Locked Loop for Network Time Synchronization with Parallel FLL and PLL." Proceedings of the 12th International IEEE Symposium on Precision Clock Synchronization for Measurement, Control, and Communication, ISPCS 2018, Geneva, CHE IEEE Computer Society, 2018.
BibTeX: Download