Darne B, Filsinger M, Bosio A, Deleruyelle D, O'Connor I, Vilquin B, Marchand C (2025)
Publication Language: English
Publication Type: Conference contribution, Conference Contribution
Publication year: 2025
Ferroelectric memory devices have emerged as a
promising class of non-volatile memory technologies, offering
a unique combination of high-speed operation, low power
consumption, and good endurance compared to conventional
flash memory. These devices leverage the bistable polarization
states of ferroelectric materials to store data, enabling non-
volatile retention while maintaining fast read/write capabilities.
The discovery of hafnium-based ferroelectric materials that are
fully CMOS compatible and exhibit robust ferroelectricity at
nanoscale dimensions has further enhanced their integration and
scalability potential. For IoT devices, which require non-volatile
state retention under constrained power budgets and frequent
interruptions, we propose a novel FeAND memory cell designed
to serve as a non-volatile backup for volatile memory. Unlike
conventional ferroelectric memories that rely on current sensing,
our design directly outputs a voltage signal, eliminating the need
for sensing circuits. The cell exhibits a logical AND-like behavior,
enabled by an innovative read scheme based on a CMOS inverter.
The cell can function as both a non-volatile memory element and
a logic gate where one input is permanently stored as a polar-
ization state. This dual functionality enables novel Computing-
in-Memory architectures by embedding logic operations directly
within the memory array. We validate our design using Cadence
Spectre simulations with the GlobalFoundries 28SLP technology.
APA:
Darne, B., Filsinger, M., Bosio, A., Deleruyelle, D., O'Connor, I., Vilquin, B., & Marchand, C. (2025). Non-Volatile Ferroelectric-AND (FeAND) Memory Cell Design. In Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2025). Puerto Varas, CL.
MLA:
Darne, Basile, et al. "Non-Volatile Ferroelectric-AND (FeAND) Memory Cell Design." Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2025), Puerto Varas 2025.
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