High-Performance, Area-Efficient and Predictable Matrix Multiplication for ASIC
Almeeva L, Lehnert A, Müller R, Reichenbach M (2025)
Publication Type: Conference contribution
Publication year: 2025
Publisher: Institute of Electrical and Electronics Engineers Inc.
Pages Range: 182-183
Conference Proceedings Title: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Event location: Vancouver, BC
ISBN: 9798331595524
DOI: 10.1109/ASAP65064.2025.00042
Abstract
With Deep Learning dominating modern applications, area-efficient and simultaneously high through-put acceleration of inference has become a crucial application. Constant Matrix Vector Multiplication (CMVM) dominates the computational complexity of these workloads, and its efficient acceleration is essential. Our proposed architecture introduces a groundbreaking extension to Computation Coding for dataflow architectures, achieving a 2.3× performance boost for small matrices and paving the way for more efficient Deep Learning inference at a performance of up to 93.52 GOP/s using a single core.
Authors with CRIS profile
Involved external institutions
Germany (DE)How to cite
APA:
Almeeva, L., Lehnert, A., Müller, R., & Reichenbach, M. (2025). High-Performance, Area-Efficient and Predictable Matrix Multiplication for ASIC. In Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors (pp. 182-183). Vancouver, BC, CA: Institute of Electrical and Electronics Engineers Inc..
MLA:
Almeeva, Liliia, et al. "High-Performance, Area-Efficient and Predictable Matrix Multiplication for ASIC." Proceedings of the 36th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2025, Vancouver, BC Institute of Electrical and Electronics Engineers Inc., 2025. 182-183.
BibTeX: Download