A 12-Bit 6-GS/s Time-Interleaved SAR ADC with On-Chip Mismatch Calibration in 28nm CMOS Technology

Linnhoff S, Buballa F, Reinhold M, Spanl R, Sippel E, Gerfers F (2025)

Publication Language: English

Publication Type: Conference contribution

Publication year: 2025

Publisher: Institute of Electrical and Electronics Engineers Inc.

Pages Range: 143-146

Conference Proceedings Title: 2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Event location: San Francisco, CA US

ISBN: 979-8-3315-1412-9

DOI: 10.1109/RFIC61188.2025.11082807

Abstract

This article presents a wideband 12 bit 6 GS/s time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a 28 nm CMOS technology addressing FMCW based radar, as well as instrumentation applications demanding excellent ADC linearity. The proposed ADC makes use of a wideband front-end featuring two subsequent ranks of pseudo-differential push-pull input buffers to distribute the input signal to 1912 bit 375 MS/s SAR-ADC lanes. Each SAR-ADC lane takes advantage of a sub-2 radix split CDAC with a 9% overrange, a distributed sample switch implemented as an isolating T-switch and a fully loop-unrolled comparator architecture. Furthermore, the ADC system features an on-chip digital calibration engine to correct inter-channel mismatch effects such as gain, offset and sample-phase mismatch. Measurement results reveal an SNDR and SFDR of 50 dB and 62.8 dBc respectively for a 1 Vppd single tone sine wave input signal across the entire 3 GHz Nyquist-band with an HD3 of 72.7 dBc at Nyquist. The complete ADC system draws 2.5 W from four power supplies (1 V, 1.8 V, 2.5 V and -1.3 V), resulting in a Schreier Figure-of-Merit (FoMs) of 145/141 dB for low and high-frequency inputs respectively.

Authors with CRIS profile

Erik Sippel Lehrstuhl für Hochfrequenztechnik (LHFT)

Involved external institutions

Technische Universität Berlin DE Germany (DE) Robert Bosch GmbH DE Germany (DE)

How to cite

APA:

Linnhoff, S., Buballa, F., Reinhold, M., Spanl, R., Sippel, E., & Gerfers, F. (2025). A 12-Bit 6-GS/s Time-Interleaved SAR ADC with On-Chip Mismatch Calibration in 28nm CMOS Technology. In Jane Gu, Kenichi Okada (Eds.), 2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (pp. 143-146). San Francisco, CA, US: Institute of Electrical and Electronics Engineers Inc..

MLA:

Linnhoff, Sebastian, et al. "A 12-Bit 6-GS/s Time-Interleaved SAR ADC with On-Chip Mismatch Calibration in 28nm CMOS Technology." Proceedings of the 2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025, San Francisco, CA Ed. Jane Gu, Kenichi Okada, Institute of Electrical and Electronics Engineers Inc., 2025. 143-146.

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