Weninger J, Probst F, Engelmann A, Spielberger A, Schrotz AM, Weigel R, Franchi N (2026)
Publication Language: English
Publication Status: Published
Publication Type: Conference contribution, Conference Contribution
Future Publication Type: Conference contribution
Publication year: 2026
Pages Range: 1-3
Event location: Jeju Island, Korea
DOI: 10.1109/APMC65046.2025.11378154
This work presents the design of an energy-efficient 2:1 digital multiplexer (MUX) utilizing true single-phase clocking (TSPC) logic, implemented in a 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. Targeted for high-speed serial link applications, the proposed MUX achieves a maximum output data rate of 36 Gb/s while consuming only 562 µW of power at peak operation. This corresponds to a figure of merit (FoM) of 15.6 fJ/bit, demonstrating strong energy efficiency. The design occupies a compact core area of just 13 µm², making it well-suited for area-constrained systems. Compared to other recent digital MUX designs, the proposed implementation offers a compelling balance of speed, power, and area efficiency for modern high-performance interfaces.
APA:
Weninger, J., Probst, F., Engelmann, A., Spielberger, A., Schrotz, A.-M., Weigel, R., & Franchi, N. (2026). A 36 Gbit/s 15.6 fJ/Bit FoM TSPC 2:1 Multiplexer for High-Speed Serial Links in 22 nm FDSOI. In Proceedings of the APMC 2025 (pp. 1-3). Jeju Island, Korea, KR.
MLA:
Weninger, Jonas, et al. "A 36 Gbit/s 15.6 fJ/Bit FoM TSPC 2:1 Multiplexer for High-Speed Serial Links in 22 nm FDSOI." Proceedings of the APMC 2025, Jeju Island, Korea 2026. 1-3.
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