PSumSim: A Simulator for Partial-Sum Quantization in Analog Matrix-Vector Multipliers

Conrad J, Wilhelmstätter S, Mandry H, Kässer P, Abdelaal A, Asthana R, Belagiannis V, Ortmanns M (2025)

Publication Type: Conference contribution

Publication year: 2025

Journal

Proceedings - IEEE International Symposium on Circuits and Systems Institute of Electrical and Electronics Engineers

Publisher: Institute of Electrical and Electronics Engineers Inc.

Conference Proceedings Title: Proceedings - IEEE International Symposium on Circuits and Systems

Event location: London GB

ISBN: 9798350356830

DOI: 10.1109/ISCAS56072.2025.11043442

Abstract

As AI and its applications evolve, efficient hardware is required to run the novel algorithms. Compute platforms with a high degree of parallelism, such as matrix-vector multipliers, meet the need to process large homogeneous loads of operations. However, most of the matrix-vector multiplications required by the AI algorithms are larger than what the actual hardware supports. The operations must therefore be tiled into blocks that fit on the given hardware. Finally, the partial sums generated by the hardware for each tile must be accumulated or concatenated into the complete result. Especially with mixed-signal compute-in-memory architectures, this can lead to quantization on two levels. First, an ADC quantizes the partial sums generated for each tile. Then, the algorithm performs another quantization of the final result to limit bitwidth and resource consumption in adjacent computations. While quantizing only the partial sums or only the final results has been studied extensively, the combination of the two has yet to be investigated. This work introduces a simulator to understand the effects of quantization caused by multiple quantization steps on different levels. It is based on a generic, stochastic representation of value probabilities using histograms. Common operations such as scaling, rounding, and accumulation are implemented in this representation, allowing the effect of quantization to be studied in a matrix-vector-multiplier application. It is shown, that the selection of tilesize, ADC bitwidth and clipping technique form a complex trade-off, which can be solved using PSumSim. PSumSim is available under https://github.com/Joschua-Conrad/PSumSim.

Authors with CRIS profile

Rohan Asthana Professur für Maschinelles Lernen in der Signalverarbeitung Vasileios Belagiannis Professur für Maschinelles Lernen in der Signalverarbeitung

Involved external institutions

Universität Ulm DE Germany (DE)

How to cite

APA:

Conrad, J., Wilhelmstätter, S., Mandry, H., Kässer, P., Abdelaal, A., Asthana, R.,... Ortmanns, M. (2025). PSumSim: A Simulator for Partial-Sum Quantization in Analog Matrix-Vector Multipliers. In Proceedings - IEEE International Symposium on Circuits and Systems. London, GB: Institute of Electrical and Electronics Engineers Inc..

MLA:

Conrad, Joschua, et al. "PSumSim: A Simulator for Partial-Sum Quantization in Analog Matrix-Vector Multipliers." Proceedings of the 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025, London Institute of Electrical and Electronics Engineers Inc., 2025.

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