A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

Andersson O, Mohammadi B, Meinerzhagen P, Rodrigues JN (2014)

Publication Type: Conference contribution

Publication year: 2014

Publisher: IEEE Computer Society

Pages Range: 243-246

Conference Proceedings Title: European Solid-State Circuits Conference

Event location: Venezia Lido, ITA

ISBN: 9781479956944

DOI: 10.1109/ESSCIRC.2014.6942067

Abstract

A 128×32 bit ultra-low power (ULP) memory with one read and one write port is presented. A full-custom standard-cell compliant dual-bit latch with two integrated NAND-gates was designed. The NAND-gate realizes the first stage of a read multiplexer. A dense layout reduces the physical cell area by 56 %, compared to a pure commercial standard-cell equivalent. Effectively, an overall memory area reduction of 32%is achieved. The gates are integrated into a digital standard-cell based memory (SCM) flow. Silicon measurements show correct read and write operation deep in the subthreshold domain (sub-VT), down to 370mV, and data is retained down to 320mV. At the energy minimum voltage (450 mV) the memory dissipates 35 fJ/operation.

Involved external institutions

Lund University / Lunds universitet SE Sweden (SE) École Polytechnique Fédérale de Lausanne (EPFL) CH Switzerland (CH)

How to cite

APA:

Andersson, O., Mohammadi, B., Meinerzhagen, P., & Rodrigues, J.N. (2014). A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. In Pietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso (Eds.), European Solid-State Circuits Conference (pp. 243-246). Venezia Lido, ITA: IEEE Computer Society.

MLA:

Andersson, Oskar, et al. "A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS." Proceedings of the 40th European Solid-State Circuit Conference, ESSCIRC 2014, Venezia Lido, ITA Ed. Pietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso, IEEE Computer Society, 2014. 243-246.

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