A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems
Hosseini-Nejad H, Jannesari A, Sodagar AM, Rodrigues JN (2015)
Publication Type: Journal article
Publication year: 2015
Journal
Book Volume: 43
Pages Range: 489-501
Journal Issue: 4
DOI: 10.1002/cta.1955
Abstract
A 128-channel neural signal processor for implantable neural recording microsystems is presented. The processor compresses the neural information of 128 simultaneous recording channels using discrete cosine transform, achieving a compression factor of 69 at the expense of a 5.6% root mean square error. The proposed processor is implemented on register transfer level and synthesized in a 65-nm complementary metal-oxide semiconductor process. The post-layout simulated power consumption at 1.2 V is 33.06 μW (258 nW per channel) at an area cost of 0.46 mm2.
Involved external institutions
Tarbiat Modares University
Iran, Islamic Republic of (IR)
Khajeh Nasir Toosi University of Technology (KNTU) / دانشگاه صنعتی خواجه نصيرالدين طوسی
Iran, Islamic Republic of (IR)
Lund University / Lunds universitet
Sweden (SE)
Iran, Islamic Republic of (IR)
Khajeh Nasir Toosi University of Technology (KNTU) / دانشگاه صنعتی خواجه نصيرالدين طوسی
Iran, Islamic Republic of (IR)
Lund University / Lunds universitet
Sweden (SE)
How to cite
APA:
Hosseini-Nejad, H., Jannesari, A., Sodagar, A.M., & Rodrigues, J.N. (2015). A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems. International Journal of Circuit Theory and Applications, 43(4), 489-501. https://doi.org/10.1002/cta.1955
MLA:
Hosseini-Nejad, Hossein, et al. "A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems." International Journal of Circuit Theory and Applications 43.4 (2015): 489-501.
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