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A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS

Andersson O, Rodrigues JN (2015)

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Publication Type: Conference contribution

Publication year: 2015

Journal

Publisher: Institute of Electrical and Electronics Engineers Inc.

Book Volume: 2015-July

Pages Range: 2628-2631

Conference Proceedings Title: Proceedings - IEEE International Symposium on Circuits and Systems

Event location: Lisbon, PRT

ISBN: 9781479983919

DOI: 10.1109/ISCAS.2015.7169225

Abstract

A real-time atrial fibrillation (AF) detector that detects episodes with statistical methods is fabricated in a 65nm high-VT CMOS process. Detection sensitivity of 94.9 % and specificity of 95.8 % are achieved for the commonly used MIT-BIH AF database. The architecture is optimized for clock- and power-gating. The design of full-custom power switches limits the power-gating area overhead to 6%. The core energy dissipation at the energy minimum point is 0.56 pJ/operation using powergates at a supply voltage of 0.4V. Targeting a medical implant operation at 37°C results in a speed increase of 1.5X at a cost of 22% higher energy dissipation. Correct operation is observed down to 0.29V. A core energy reduction of 71% was attained with power-gating.

Involved external institutions

How to cite

APA:

Andersson, O., & Rodrigues, J.N. (2015). A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 2628-2631). Lisbon, PRT: Institute of Electrical and Electronics Engineers Inc..

MLA:

Andersson, Oskar, and Joachim Neves Rodrigues. "A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS." Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, PRT Institute of Electrical and Electronics Engineers Inc., 2015. 2628-2631.

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