TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

Constantin J, Dogan A, Andersson O, Meinerzhagen P, Rodrigues JN, Atienza D, Burg A (2015)

Publication Type: Conference contribution

Publication year: 2015

Publisher: IEEE Computer Society

Book Volume: 07-10-October-2012

Pages Range: 159-164

Conference Proceedings Title: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

Event location: Santa Cruz, CA, USA

ISBN: 9781467326582

DOI: 10.1109/VLSI-SoC.2012.7332094

Abstract

Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ultra-low-power (ULP) CS implementation is vital for these kind of energy-limited systems. Sub-threshold (sub-VT) operation is commonly used for ULP computing, and can also be combined with CS. However, most established CS implementations can achieve either no or very limited benefit from sub-VT operation. Therefore, we propose a sub-VT application-specific instruction-set processor (ASIP), exploiting the specific operations of CS. Our results show that the proposed ASIP accomplishes 62x speed-up and 11.6x power savings with respect to an established CS implementation running on the baseline low-power processor.

Involved external institutions

École Polytechnique Fédérale de Lausanne (EPFL) CH Switzerland (CH) Lund University / Lunds universitet SE Sweden (SE)

How to cite

APA:

Constantin, J., Dogan, A., Andersson, O., Meinerzhagen, P., Rodrigues, J.N., Atienza, D., & Burg, A. (2015). TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. In IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC (pp. 159-164). Santa Cruz, CA, USA: IEEE Computer Society.

MLA:

Constantin, Jeremy, et al. "TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing." Proceedings of the IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA IEEE Computer Society, 2015. 159-164.

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